[all-commits] [llvm/llvm-project] 1e7865: [X86] SimplifyMultipleUseDemandedBitsForTargetNode...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 1e7865d94647119aab3c1b2e8ce259ca1634bc64
      https://github.com/llvm/llvm-project/commit/1e7865d94647119aab3c1b2e8ce259ca1634bc64
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-05-24 (Sun, 24 May 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/avx2-masked-gather.ll
    M llvm/test/CodeGen/X86/movmsk-cmp.ll
    M llvm/test/CodeGen/X86/pr18014.ll

  Log Message:
  -----------
  [X86] SimplifyMultipleUseDemandedBitsForTargetNode - add initial X86ISD::VSRAI handling.

This initial version only peeks through cases where we just demand the sign bit of an ashr shift, but we could generalize this further depending on how many sign bits we already have.

The pr18014.ll case is a minor annoyance - we've failed to to move the psrad/paddd after the blendvps which would have avoided the extra move, but we have still increased the ILP.