[all-commits] [llvm/llvm-project] 9c53ac: [mlir][rocdl] Exposing buffer load/store intrinsic

[Zhuoran Yin via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 9c53ac08de7c5bfefab6e6c80127e6774070411c
      https://github.com/llvm/llvm-project/commit/9c53ac08de7c5bfefab6e6c80127e6774070411c
  Author: jerryyin <zhuoryin at amd.com>
  Date:   2020-05-21 (Thu, 21 May 2020)

  Changed paths:
    M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
    M mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp
    M mlir/lib/Target/LLVMIR/ConvertToROCDLIR.cpp
    M mlir/test/Dialect/LLVMIR/rocdl.mlir
    M mlir/test/Target/rocdl.mlir

  Log Message:
  -----------
  [mlir][rocdl] Exposing buffer load/store intrinsic

Summary:
* Updated ROCDLOps tablegen
* Added parsing and printing function for new intrinsic
* Added unit tests

Reviewers: ftynse

Subscribers: mehdi_amini, rriddle, jpienaar, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, stephenneuendorffer, Joonsoo, grosul1, frgossen, Kayjukh, jurahul, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80233