[all-commits] [llvm/llvm-project] a45fb1: [mlir][Affine] Introduce affine memory interfaces

[Diego Caballero via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: a45fb1942fc5d21dfcdc37b99ab98778d3b16b79
      https://github.com/llvm/llvm-project/commit/a45fb1942fc5d21dfcdc37b99ab98778d3b16b79
  Author: Diego Caballero <diego.caballero at intel.com>
  Date:   2020-05-19 (Tue, 19 May 2020)

  Changed paths:
    A mlir/include/mlir/Dialect/Affine/IR/AffineMemoryOpInterfaces.h
    A mlir/include/mlir/Dialect/Affine/IR/AffineMemoryOpInterfaces.td
    M mlir/include/mlir/Dialect/Affine/IR/AffineOps.h
    M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
    M mlir/include/mlir/Dialect/Affine/IR/CMakeLists.txt
    M mlir/lib/Analysis/AffineAnalysis.cpp
    M mlir/lib/Analysis/Utils.cpp
    A mlir/lib/Dialect/Affine/IR/AffineMemoryOpInterfaces.cpp
    M mlir/lib/Dialect/Affine/IR/CMakeLists.txt
    M mlir/lib/Transforms/LoopFusion.cpp
    M mlir/test/lib/Transforms/TestMemRefBoundCheck.cpp

  Log Message:
  -----------
  [mlir][Affine] Introduce affine memory interfaces

This patch introduces interfaces for read and write ops with affine
restrictions. I used `read`/`write` intead of `load`/`store` for the
interfaces so that they can also be implemented by dma ops.
For now, they are only implemented by affine.load, affine.store,
affine.vector_load and affine.vector_store.

For testing purposes, this patch also migrates affine loop fusion and
required analysis to use the new interfaces. No other changes are made
beyond that.

Co-authored-by: Alex Zinenko <zinenko at google.com>

Reviewed By: bondhugula, ftynse

Differential Revision: https://reviews.llvm.org/D79829