[all-commits] [llvm/llvm-project] f3164f: [ARM] Only produce qadd8b under hasV6Ops

[David Green via All-commits]

  Branch: refs/heads/release/10.x
  Home:   https://github.com/llvm/llvm-project
  Commit: f3164f752708753323e2e6a8d17e703cfeb69be6
      https://github.com/llvm/llvm-project/commit/f3164f752708753323e2e6a8d17e703cfeb69be6
  Author: David Green <david.green at arm.com>
  Date:   2020-05-19 (Tue, 19 May 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/test/CodeGen/ARM/sadd_sat.ll

  Log Message:
  -----------
  [ARM] Only produce qadd8b under hasV6Ops

When compiling for a arm5te cpu from clang, the +dsp attribute is set.
This meant we could try and generate qadd8 instructions where we would
end up having no pattern. I've changed the condition here to be hasV6Ops
&& hasDSP, which is what other parts of ARMISelLowering seem to use for
similar instructions.

Fixed PR45677.

Differential Revision: https://reviews.llvm.org/D78877

(cherry picked from commit 8807139026b64ac40163bb255dad38a1d8054f08)