[all-commits] [llvm/llvm-project] 2b0b9b: [X86] Fix a regression caused by moving combineLoo...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 2b0b9b1148c205dfd73c70d195f51ef9895e2307
      https://github.com/llvm/llvm-project/commit/2b0b9b1148c205dfd73c70d195f51ef9895e2307
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86PartialReduction.cpp
    M llvm/test/CodeGen/X86/madd.ll

  Log Message:
  -----------
  [X86] Fix a regression caused by moving combineLoopMAddPattern to IR

When I moved combineLoopMAddPattern to an IR pass. I didn't match the behavior of canReduceVMulWidth that was used in the SelectionDAG version. canReduceVMulWidth just calls computeSignBits and assumes a truncate is always profitable. The version I put in IR just looks for constants and zext/sext. Though I neglected to check the number of bits in input of the zext/sext.

This patch adds a check for the number of input bits to the sext/zext. And it adds a special case for add/sub with zext/sext inputs which can be handled by combineTruncatedArithmetic. Match the original SelectionDAG behavior appears to be a regression in some cases if the truncate isn't removed and becomes pack and permq. So enabling only this specific case is the conservative approach.

Differential Revision: https://reviews.llvm.org/D79909