[all-commits] [llvm/llvm-project] cac6a2: [TableGen] Fix register class handling in TableGen...

[Victor Campos via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: cac6a26f38131371450b6fb55e75ba7299228afe
      https://github.com/llvm/llvm-project/commit/cac6a26f38131371450b6fb55e75ba7299228afe
  Author: Victor Campos <victor.campos at arm.com>
  Date:   2020-05-13 (Wed, 13 May 2020)

  Changed paths:
    A llvm/test/TableGen/dag-isel-regclass-emit-enum.td
    M llvm/utils/TableGen/DAGISelMatcherGen.cpp

  Log Message:
  -----------
  [TableGen] Fix register class handling in TableGen's DAG ISel Matcher Generator

Summary:
In TableGen's instruction selection table generator, references to
register classes were handled by generating a matcher table entry in the
form of "EmitStringInteger, MVT::i32, 'RegisterClassID'". This ID is in
fact the enum integer value corresponding to the register class.

However, both the table generator and the table consumer
(SelectionDAGISel) assume that this ID is less than or equal to 127,
i.e. at most 7 bits. Values greater than this threshold cause completely
wrong behaviours in the instruction selection process.

This patch adds a check to determine if the enum integer value is
greater than the limit of 127. In finding so, the generator emits an
"EmitInteger" instead, which properly supports values with arbitrary
sizes.

Commit f8d044bbcfdc9e1ddc02247ffb86fe39e1f277f0 fixed the very same bug
for register subindices. The present patch now extends this cover to
register classes.

Reviewers: rampitec

Reviewed By: rampitec

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D79705