[all-commits] [llvm/llvm-project] 077d2d: [CodeGen][SVE] Add patterns for whole vector predi...

[sdesmalen-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 077d2d6802efefe6680cbae78f90e90ef7f04134
      https://github.com/llvm/llvm-project/commit/077d2d6802efefe6680cbae78f90e90ef7f04134
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2020-05-12 (Tue, 12 May 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    A llvm/test/CodeGen/AArch64/select-sve.ll

  Log Message:
  -----------
  [CodeGen][SVE] Add patterns for whole vector predicate select

Added patterns to implement `select i1 %p, <vty> %a, <vty> %b`

Reviewed By: efriedma

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D79356