[all-commits] [llvm/llvm-project] 3bcd3d: [CodeGen][SVE] Lowering of shift operations with s...

[kmclaughlin-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 3bcd3dd4734d987176d551fcccc80e70d3e16983
      https://github.com/llvm/llvm-project/commit/3bcd3dd4734d987176d551fcccc80e70d3e16983
  Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
  Date:   2020-05-07 (Thu, 07 May 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
    M llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll

  Log Message:
  -----------
  [CodeGen][SVE] Lowering of shift operations with scalable types

Summary:
Adds AArch64ISD nodes for:
 - SHL_PRED (logical shift left)
 - SHR_PRED (logical shift right)
 - SRA_PRED (arithmetic shift right)

Existing patterns for unpredicated left shift by immediate
have also been moved into the appropriate multiclasses
in SVEInstrFormats.td.

Reviewers: sdesmalen, efriedma, ctetreau, huihuiz, rengolin

Reviewed By: efriedma

Subscribers: huihuiz, tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D79478