[all-commits] [llvm/llvm-project] a31f4c: [SVE][CodeGen] Fix legalisation for scalable types

[kmclaughlin-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: a31f4c52bf85a5a3e11d155c98394accef9d2ca9
      https://github.com/llvm/llvm-project/commit/a31f4c52bf85a5a3e11d155c98394accef9d2ca9
  Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
  Date:   2020-05-07 (Thu, 07 May 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/CodeGen/TargetLoweringBase.cpp
    M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll

  Log Message:
  -----------
  [SVE][CodeGen] Fix legalisation for scalable types

Summary:
This patch handles illegal scalable types when lowering IR operations,
addressing several places where the value of isScalableVector() is
ignored.

For types such as <vscale x 8 x i32>, this means splitting the
operations. In this example, we would split it into two
operations of type <vscale x 4 x i32> for the low and high halves.

In cases such as <vscale x 2 x i32>, the elements in the vector
will be promoted. In this case they will be promoted to
i64 (with a vector of type <vscale x 2 x i64>)

Reviewers: sdesmalen, efriedma, huntergr

Reviewed By: efriedma

Subscribers: david-arm, tschuett, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78812