[all-commits] [llvm/llvm-project] 2c8546: [AArch64][SVE] Implement lowering for SIGN_EXTEND ...

[Eli Friedman via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 2c8546107a91a7b9a31791452712676937df54fe
      https://github.com/llvm/llvm-project/commit/2c8546107a91a7b9a31791452712676937df54fe
  Author: Eli Friedman <efriedma at quicinc.com>
  Date:   2020-05-06 (Wed, 06 May 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/sve-fcmp.ll
    A llvm/test/CodeGen/AArch64/sve-sext-zext.ll

  Log Message:
  -----------
  [AArch64][SVE] Implement lowering for SIGN_EXTEND etc. of SVE predicates.

Now using patterns, since there's a single-instruction lowering. (We
could convert to VSELECT and pattern-match that, but there doesn't seem
to be much point.)

I think this might be the first instruction to use nested multiclasses
this way? It seems like a good way to reduce duplication between
different integer widths. Let me know if it seems like an improvement.

Also, while I'm here, fix the return type of SETCC so we don't try to
merge a sign-extend with a SETCC.

Differential Revision: https://reviews.llvm.org/D79193