[all-commits] [llvm/llvm-project] 85aff8: [RISCV] Update debug scratch register names

[pzhengqc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 85aff8a4e49d2bcd143ea1da5b42ced9e4cd2e39
      https://github.com/llvm/llvm-project/commit/85aff8a4e49d2bcd143ea1da5b42ced9e4cd2e39
  Author: Pengxuan Zheng <pzheng at quicinc.com>
  Date:   2020-05-05 (Tue, 05 May 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/RISCVSystemOperands.td
    M llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
    M llvm/test/MC/RISCV/machine-csr-names.s

  Log Message:
  -----------
  [RISCV] Update debug scratch register names

Summary:
The RISC-V debug register was named dscratch in a previous draft of the RISC-V
debug mode spec. The number of registers has been increased to 2 in the latest
ratified version of the debug mode spec and the registers were named dscratch0
and dscratch1. We still support using the old register name "dscratch", but it
would be disassembled as "dscratch0" with this change.

Reviewers: apazos, asb, lenary, luismarques

Reviewed By: asb

Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, sameer.abuasal, evandro, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78764