[all-commits] [llvm/llvm-project] 19f5da: [SVE][Codegen] Lower legal min & max operations
kmclaughlin-arm via All-commits
all-commits at lists.llvm.org
Mon May 4 04:49:58 PDT 2020
Branch: refs/heads/master
Home: https://github.com/llvm/llvm-project
Commit: 19f5da9c1d698653f942b504544a73b85b1e703c
https://github.com/llvm/llvm-project/commit/19f5da9c1d698653f942b504544a73b85b1e703c
Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: 2020-05-04 (Mon, 04 May 2020)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll
Log Message:
-----------
[SVE][Codegen] Lower legal min & max operations
Summary:
This patch adds AArch64ISD nodes for [S|U]MIN_PRED
and [S|U]MAX_PRED, and lowers both SVE intrinsics and
IR operations for min and max to these nodes.
There are two forms of these instructions for SVE: a predicated
form and an immediate (unpredicated) form. The patterns
which existed for the latter have been updated to match a
predicated node with an immediate and map this
to the immediate instruction.
Reviewers: sdesmalen, efriedma, dancgr, rengolin
Reviewed By: efriedma
Subscribers: huihuiz, tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D79087
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