[all-commits] [llvm/llvm-project] 6bfde0: [SystemZ] Simplify register parsing in AsmParser

[Ulrich Weigand via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 6bfde063f0a7c336fb4c82a4b72da9b3812d31d0
      https://github.com/llvm/llvm-project/commit/6bfde063f0a7c336fb4c82a4b72da9b3812d31d0
  Author: Ulrich Weigand <ulrich.weigand at de.ibm.com>
  Date:   2020-04-29 (Wed, 29 Apr 2020)

  Changed paths:
    M llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

  Log Message:
  -----------
  [SystemZ] Simplify register parsing in AsmParser

Remove redundant Group and Regs arguments from parseRegister
and eliminate one of its overloaded versions.

Remove redundant Regs argument from parseAddress.

NFC intended.


  Commit: e1de2773a534957305d7a559c6d88c4b5ac354e2
      https://github.com/llvm/llvm-project/commit/e1de2773a534957305d7a559c6d88c4b5ac354e2
  Author: Ulrich Weigand <ulrich.weigand at de.ibm.com>
  Date:   2020-04-29 (Wed, 29 Apr 2020)

  Changed paths:
    M llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
    M llvm/test/MC/SystemZ/regs-bad.s
    M llvm/test/MC/SystemZ/regs-good.s

  Log Message:
  -----------
  [SystemZ] Allow specifying plain register numbers in AsmParser

For compatibility with other assemblers on the platform, allow
using just plain integer register numbers in all places where a
register operand is expected.

Bug: llvm.org/PR45582


Compare: https://github.com/llvm/llvm-project/compare/cecee111e44f...e1de2773a534