[all-commits] [llvm/llvm-project] 476ba8: [SveEmitter] Add builtins for zero/sign extension ...

[sdesmalen-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 476ba8127bfa4553bf5ce1654cd844803e8d6dea
      https://github.com/llvm/llvm-project/commit/476ba8127bfa4553bf5ce1654cd844803e8d6dea
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2020-04-28 (Tue, 28 Apr 2020)

  Changed paths:
    M clang/include/clang/Basic/arm_sve.td
    A clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_extb.c
    A clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_exth.c
    A clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_extw.c
    A clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rbit.c
    A clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revb.c
    A clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revh.c
    A clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revw.c

  Log Message:
  -----------
  [SveEmitter] Add builtins for zero/sign extension and bit/byte reversal.

This patch adds builtins for predicated unary builtins
svext[bhw] and svrev[bhw] and svrbit.