[all-commits] [llvm/llvm-project] d9e174: [X86][SSE] getFauxShuffle - account for PEXTW/PEXT...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: d9e174dbf766bb271aeba79f265e766ff31ef9f2
      https://github.com/llvm/llvm-project/commit/d9e174dbf766bb271aeba79f265e766ff31ef9f2
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-04-27 (Mon, 27 Apr 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/vector-shuffle-combining.ll

  Log Message:
  -----------
  [X86][SSE] getFauxShuffle - account for PEXTW/PEXTB implicit zero-extension

The insert(truncate/extend(extract(vec0,c0)),vec1,c1) case in rGacbc5ede99 wasn't combining the 'mineltsize' with the src vector elt size which may be smaller due to implicit extension during extraction.

Reduced from test case provided by @mstorsjo