[all-commits] [llvm/llvm-project] 79702d: [RISCV] Add instruction definition for dret

[pzhengqc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 79702dd349f31c0c67bf35f36435fdc843fcd052
      https://github.com/llvm/llvm-project/commit/79702dd349f31c0c67bf35f36435fdc843fcd052
  Author: Pengxuan Zheng <pzheng at quicinc.com>
  Date:   2020-04-24 (Fri, 24 Apr 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    A llvm/test/MC/RISCV/debug-valid.s

  Log Message:
  -----------
  [RISCV] Add instruction definition for dret

Summary:
The instruction dret is used to return from debug mode and is defined in the
RISC-V debug mode spec.

https://github.com/riscv/riscv-opcodes/blob/master/opcodes-system

Reviewers: apazos, asb, lenary, luismarques

Reviewed By: apazos

Subscribers: jfb, hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, sameer.abuasal, evandro, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78583