[all-commits] [llvm/llvm-project] 0312b9: [llvm] NFC: Fix trivial typo in rst and td files

[Kazuaki Ishizaki via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 0312b9f55077021141808e6d3e5ccc6f4f7b6ae6
      https://github.com/llvm/llvm-project/commit/0312b9f55077021141808e6d3e5ccc6f4f7b6ae6
  Author: Kazuaki Ishizaki <ishizaki at jp.ibm.com>
  Date:   2020-04-23 (Thu, 23 Apr 2020)

  Changed paths:
    M llvm/docs/AMDGPUUsage.rst
    M llvm/docs/Extensions.rst
    M llvm/docs/HowToUseInstrMappings.rst
    M llvm/docs/LangRef.rst
    M llvm/docs/ProgrammersManual.rst
    M llvm/docs/Proposals/GitHubMove.rst
    M llvm/docs/TableGen/LangRef.rst
    M llvm/docs/tutorial/BuildingAJIT2.rst
    M llvm/include/llvm/IR/IntrinsicsAArch64.td
    M llvm/include/llvm/IR/IntrinsicsARM.td
    M llvm/include/llvm/IR/IntrinsicsPowerPC.td
    M llvm/include/llvm/IR/IntrinsicsX86.td
    M llvm/include/llvm/Target/Target.td
    M llvm/include/llvm/Target/TargetItinerary.td
    M llvm/include/llvm/Target/TargetSchedule.td
    M llvm/include/llvm/Target/TargetSelectionDAG.td
    M llvm/lib/Target/AArch64/AArch64.td
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AArch64SystemOperands.td
    M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
    M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
    M llvm/lib/Target/AMDGPU/BUFInstructions.td
    M llvm/lib/Target/AMDGPU/DSInstructions.td
    M llvm/lib/Target/AMDGPU/FLATInstructions.td
    M llvm/lib/Target/AMDGPU/MIMGInstructions.td
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/lib/Target/AMDGPU/SISchedule.td
    M llvm/lib/Target/AMDGPU/SMInstructions.td
    M llvm/lib/Target/AMDGPU/SOPInstructions.td
    M llvm/lib/Target/AMDGPU/VIInstructions.td
    M llvm/lib/Target/AMDGPU/VOP1Instructions.td
    M llvm/lib/Target/AMDGPU/VOP2Instructions.td
    M llvm/lib/Target/AMDGPU/VOP3Instructions.td
    M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
    M llvm/lib/Target/AMDGPU/VOPCInstructions.td
    M llvm/lib/Target/AMDGPU/VOPInstructions.td
    M llvm/lib/Target/ARC/ARCInstrInfo.td
    M llvm/lib/Target/ARM/ARMInstrCDE.td
    M llvm/lib/Target/ARM/ARMInstrInfo.td
    M llvm/lib/Target/ARM/ARMInstrMVE.td
    M llvm/lib/Target/ARM/ARMInstrNEON.td
    M llvm/lib/Target/ARM/ARMInstrThumb.td
    M llvm/lib/Target/ARM/ARMInstrThumb2.td
    M llvm/lib/Target/ARM/ARMScheduleSwift.td
    M llvm/lib/Target/Hexagon/HexagonIICScalar.td
    M llvm/lib/Target/Hexagon/HexagonInstrFormats.td
    M llvm/lib/Target/Hexagon/HexagonInstrFormatsV65.td
    M llvm/lib/Target/Hexagon/HexagonPseudo.td
    M llvm/lib/Target/Mips/MicroMipsInstrFormats.td
    M llvm/lib/Target/Mips/MicroMipsInstrInfo.td
    M llvm/lib/Target/Mips/Mips16InstrInfo.td
    M llvm/lib/Target/Mips/MipsInstrInfo.td
    M llvm/lib/Target/PowerPC/PPC.td
    M llvm/lib/Target/PowerPC/PPCInstrInfo.td
    M llvm/lib/Target/PowerPC/PPCInstrVSX.td
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
    M llvm/lib/Target/PowerPC/PPCScheduleP9.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/Sparc/SparcCallingConv.td
    M llvm/lib/Target/Sparc/SparcInstrInfo.td
    M llvm/lib/Target/Sparc/SparcSchedule.td
    M llvm/lib/Target/SystemZ/SystemZInstrFormats.td
    M llvm/lib/Target/SystemZ/SystemZInstrVector.td
    M llvm/lib/Target/SystemZ/SystemZPatterns.td
    M llvm/lib/Target/SystemZ/SystemZProcessors.td
    M llvm/lib/Target/WebAssembly/WebAssemblyInstrCall.td
    M llvm/lib/Target/WebAssembly/WebAssemblyInstrRef.td
    M llvm/lib/Target/X86/X86.td
    M llvm/lib/Target/X86/X86InstrAVX512.td
    M llvm/lib/Target/X86/X86InstrCompiler.td
    M llvm/lib/Target/X86/X86InstrFMA.td
    M llvm/lib/Target/X86/X86InstrFPStack.td
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/lib/Target/X86/X86InstrSSE.td
    M llvm/lib/Target/X86/X86RegisterInfo.td
    M llvm/lib/Target/X86/X86SchedBroadwell.td
    M llvm/lib/Target/X86/X86SchedHaswell.td
    M llvm/lib/Target/X86/X86SchedSandyBridge.td
    M llvm/lib/Target/X86/X86SchedSkylakeClient.td
    M llvm/lib/Target/X86/X86SchedSkylakeServer.td
    M llvm/test/TableGen/ConcatenatedSubregs.td
    M llvm/test/TableGen/prep-region-processing.td

  Log Message:
  -----------
  [llvm] NFC: Fix trivial typo in rst and td files

Differential Revision: https://reviews.llvm.org/D77469