[all-commits] [llvm/llvm-project] d625b4: [AMDGPU] Add missing AReg classes

[jayfoad via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: d625b4b081f9ea2d96d5bdfc1f05925b30d8b1a3
      https://github.com/llvm/llvm-project/commit/d625b4b081f9ea2d96d5bdfc1f05925b30d8b1a3
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2020-04-22 (Wed, 22 Apr 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
    M llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

  Log Message:
  -----------
  [AMDGPU] Add missing AReg classes

Add 96-bit, 160-bit and 256-bit AReg classes to match VReg and SReg.
NFC as far as I know, but it may avoid weird legalization problems.

Differential Revision: https://reviews.llvm.org/D78348


  Commit: dbdffe3ee9d6fd4739bef5f03e61f052a95e72ca
      https://github.com/llvm/llvm-project/commit/dbdffe3ee9d6fd4739bef5f03e61f052a95e72ca
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2020-04-22 (Wed, 22 Apr 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
    R llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte-xfail.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
    R llvm/test/CodeGen/AMDGPU/GlobalISel/zextload-xfail.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
    M llvm/test/CodeGen/AMDGPU/ipra-regmask.ll

  Log Message:
  -----------
  [AMDGPU] Add 192-bit register classes

Differential Revision: https://reviews.llvm.org/D78312


Compare: https://github.com/llvm/llvm-project/compare/b2f06bd20bde...dbdffe3ee9d6