[all-commits] [llvm/llvm-project] b4b9fa: [AArch64] Fix MIR tests with invalid live-ins.

[Eli Friedman via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: b4b9faa120f8790eb06ee0de4751ec261ad2e331
      https://github.com/llvm/llvm-project/commit/b4b9faa120f8790eb06ee0de4751ec261ad2e331
  Author: Eli Friedman <efriedma at quicinc.com>
  Date:   2020-04-21 (Tue, 21 Apr 2020)

  Changed paths:
    M llvm/test/CodeGen/AArch64/jump-table-compress.mir
    M llvm/test/CodeGen/AArch64/machine-copy-remove.mir
    M llvm/test/CodeGen/AArch64/machine-outliner-regsave.mir
    M llvm/test/CodeGen/AArch64/machine-zero-copy-remove.mir
    M llvm/test/CodeGen/AArch64/post-ra-machine-sink.mir
    M llvm/test/CodeGen/AArch64/unreachable-emergency-spill-slot.mir
    M llvm/test/CodeGen/AArch64/wineh4.mir
    M llvm/test/CodeGen/AArch64/wineh8.mir

  Log Message:
  -----------
  [AArch64] Fix MIR tests with invalid live-ins.

A register can't be live if it isn't defined; fix issues in various
testcases.

Differential Revision: https://reviews.llvm.org/D78531


  Commit: 704293b1684828a9fdba4ca6aad0132c6cd1ec03
      https://github.com/llvm/llvm-project/commit/704293b1684828a9fdba4ca6aad0132c6cd1ec03
  Author: Eli Friedman <efriedma at quicinc.com>
  Date:   2020-04-21 (Tue, 21 Apr 2020)

  Changed paths:
    M llvm/test/CodeGen/ARM/constant-islands-split-IT.mir
    M llvm/test/CodeGen/ARM/ifcvt-size.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir
    M llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir

  Log Message:
  -----------
  [ARM] Fix MIR tests with invalid live-ins.

A register can't be live if it isn't defined; fix issues in various
testcases.

Differential Revision: https://reviews.llvm.org/D78529


Compare: https://github.com/llvm/llvm-project/compare/2e1cfd02d0f1...704293b16848