[all-commits] [llvm/llvm-project] 8bb059: [MC][Bugfix] Remove redundant parameter for relaxI...

[KanRobert via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 8bb059ab6379a7830620b9e240b817c070b35034
      https://github.com/llvm/llvm-project/commit/8bb059ab6379a7830620b9e240b817c070b35034
  Author: Shengchen Kan <shengchen.kan at intel.com>
  Date:   2020-04-21 (Tue, 21 Apr 2020)

  Changed paths:
    M llvm/include/llvm/MC/MCAsmBackend.h
    M llvm/lib/MC/MCAssembler.cpp
    M llvm/lib/MC/MCObjectStreamer.cpp
    M llvm/lib/MCA/CodeEmitter.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
    M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
    M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
    M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
    M llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h
    M llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
    M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
    M llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp
    M llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp
    M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
    M llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
    M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
    M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp
    M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
    A llvm/test/MC/RISCV/rv64-relax-all.s

  Log Message:
  -----------
  [MC][Bugfix] Remove redundant parameter for relaxInstruction

Summary:
Before this patch, `relaxInstruction` takes three arguments, the first
argument refers to the instruction before relaxation and the third
argument is the output instruction after relaxation. There are two quite
strange things:
  1) The first argument's type is `const MCInst &`, the third
  argument's type is `MCInst &`, but they may be aliased to the same
  variable
  2) The backends of ARM, AMDGPU, RISC-V, Hexagon assume that the third
  argument is a fresh uninitialized `MCInst` even if `relaxInstruction`
  may be called like `relaxInstruction(Relaxed, STI, Relaxed)` in a
  loop.

In this patch, we drop the thrid argument, and let `relaxInstruction`
directly modify the given instruction. Also, this patch fixes the bug https://bugs.llvm.org/show_bug.cgi?id=45580, which is introduced by D77851, and
breaks the assumption of ARM, AMDGPU, RISC-V, Hexagon.

Reviewers: Razer6, MaskRay, jyknight, asb, luismarques, enderby, rtaylor, colinl, bcain

Reviewed By: Razer6, MaskRay, bcain

Subscribers: bcain, nickdesaulniers, nathanchance, wuzish, annita.zhang, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, tpr, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78364