[all-commits] [llvm/llvm-project] 48879c: [llvm][CodeGen] Fix issue for SVE gather prefetch.

[Francesco Petrogalli via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 48879c02bfc40017ec7d4dcfbd920ef949b53cf6
      https://github.com/llvm/llvm-project/commit/48879c02bfc40017ec7d4dcfbd920ef949b53cf6
  Author: Francesco Petrogalli <francesco.petrogalli at arm.com>
  Date:   2020-04-17 (Fri, 17 Apr 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-prefetches-vect-base-invalid-imm-offset.ll

  Log Message:
  -----------
  [llvm][CodeGen] Fix issue for SVE gather prefetch.

Summary:
This change is fixing an issue where the dagcombine incorrectly used an addressing mode with scaled offsets (indices), instead of unscaled offsets.
Those addressing modes do not exist for `prfh` , `prfw` and `prfd`, hence we can reuse `prfb` because that has unscaled offsets, and because the pseudo-code in the XML spec suggests that the element size is not used for the amount of data that is prefetched by the instruction.

FWIW, GCC also emits a `prfb` for these cases.

Reviewers: sdesmalen, andwar, rengolin

Reviewed By: sdesmalen

Subscribers: tschuett, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78069