[all-commits] [llvm/llvm-project] 513976: [PowerPC] Ignore implicit register operands for MC...

[Zhang Kang via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 513976df2e6541a73876bac896e4d923e42413b9
      https://github.com/llvm/llvm-project/commit/513976df2e6541a73876bac896e4d923e42413b9
  Author: Kang Zhang <shkzhang at cn.ibm.com>
  Date:   2020-04-16 (Thu, 16 Apr 2020)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
    M llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir
    M llvm/test/CodeGen/PowerPC/atomics-regression.ll
    M llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll
    M llvm/test/CodeGen/PowerPC/bool-math.ll
    M llvm/test/CodeGen/PowerPC/branch_coalesce.ll
    M llvm/test/CodeGen/PowerPC/bswap64.ll
    M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
    M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
    M llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
    M llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
    M llvm/test/CodeGen/PowerPC/crbits.ll
    M llvm/test/CodeGen/PowerPC/dform-adjust.ll
    M llvm/test/CodeGen/PowerPC/expand-isel.ll
    M llvm/test/CodeGen/PowerPC/extract-and-store.ll
    M llvm/test/CodeGen/PowerPC/f128-aggregates.ll
    M llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
    M llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
    M llvm/test/CodeGen/PowerPC/funnel-shift.ll
    M llvm/test/CodeGen/PowerPC/inlineasm-i64-reg.ll
    M llvm/test/CodeGen/PowerPC/knowCRBitSpill.ll
    M llvm/test/CodeGen/PowerPC/load-and-splat.ll
    M llvm/test/CodeGen/PowerPC/loop-comment.ll
    M llvm/test/CodeGen/PowerPC/memcmp.ll
    M llvm/test/CodeGen/PowerPC/optcmp.ll
    M llvm/test/CodeGen/PowerPC/optimize-andiso.ll
    M llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
    M llvm/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll
    M llvm/test/CodeGen/PowerPC/popcnt-zext.ll
    M llvm/test/CodeGen/PowerPC/ppc-crbits-onoff.ll
    M llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
    M llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
    M llvm/test/CodeGen/PowerPC/pr25080.ll
    M llvm/test/CodeGen/PowerPC/pr33093.ll
    M llvm/test/CodeGen/PowerPC/pr35688.ll
    M llvm/test/CodeGen/PowerPC/pr45448.ll
    M llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
    M llvm/test/CodeGen/PowerPC/qpx-s-sel.ll
    M llvm/test/CodeGen/PowerPC/qpx-sel.ll
    M llvm/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll
    M llvm/test/CodeGen/PowerPC/sat-add.ll
    M llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll
    M llvm/test/CodeGen/PowerPC/select_const.ll
    M llvm/test/CodeGen/PowerPC/setcc-logic.ll
    M llvm/test/CodeGen/PowerPC/shift_mask.ll
    M llvm/test/CodeGen/PowerPC/signbit-shift.ll
    M llvm/test/CodeGen/PowerPC/simplifyConstCmpToISEL.ll
    M llvm/test/CodeGen/PowerPC/sms-cpy-1.ll
    M llvm/test/CodeGen/PowerPC/spill_p9_setb.ll
    M llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
    M llvm/test/CodeGen/PowerPC/stack-realign.ll
    M llvm/test/CodeGen/PowerPC/testBitReverse.ll
    M llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll
    M llvm/test/CodeGen/PowerPC/testComparesi32leu.ll
    M llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll
    M llvm/test/CodeGen/PowerPC/testComparesigesll.ll
    M llvm/test/CodeGen/PowerPC/testComparesigeull.ll
    M llvm/test/CodeGen/PowerPC/testComparesigtsll.ll
    M llvm/test/CodeGen/PowerPC/testComparesilesll.ll
    M llvm/test/CodeGen/PowerPC/testComparesileull.ll
    M llvm/test/CodeGen/PowerPC/testComparesiltsll.ll
    M llvm/test/CodeGen/PowerPC/testComparesllgesll.ll
    M llvm/test/CodeGen/PowerPC/testComparesllgeull.ll
    M llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll
    M llvm/test/CodeGen/PowerPC/testCompareslllesll.ll
    M llvm/test/CodeGen/PowerPC/testComparesllleull.ll
    M llvm/test/CodeGen/PowerPC/testComparesllltsll.ll
    M llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll
    M llvm/test/CodeGen/PowerPC/trunc-srl-load.ll
    M llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
    M llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
    M llvm/test/CodeGen/PowerPC/vec-min-max.ll
    M llvm/test/CodeGen/PowerPC/vec-trunc.ll
    M llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll
    M llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp_to_i_4byte_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i_to_fp_4byte_elts.ll
    M llvm/test/CodeGen/PowerPC/vsx.ll
    M llvm/test/CodeGen/PowerPC/xray-conditional-return.ll

  Log Message:
  -----------
  [PowerPC] Ignore implicit register operands for MCInst

Summary:
When doing the conversion: MachineInst -> MCInst, we should ignore the
implicit operands, it will expose more opportunity for InstiAlias.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D77118