[all-commits] [llvm/llvm-project] fae40b: [RISCV] Add MC layer support for proposed Bit Mani...

[Scott Egerton via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: fae40bd5a1d4d0ef5f60d5a441757d39a06ce077
      https://github.com/llvm/llvm-project/commit/fae40bd5a1d4d0ef5f60d5a441757d39a06ce077
  Author: Paolo Savini <paolo.savini at embecosm.com>
  Date:   2020-04-09 (Thu, 09 Apr 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    A llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    A llvm/test/MC/RISCV/compress-rv32b.s
    A llvm/test/MC/RISCV/compress-rv64b.s
    A llvm/test/MC/RISCV/rv32b-aliases-valid.s
    A llvm/test/MC/RISCV/rv32zbb-invalid.s
    A llvm/test/MC/RISCV/rv32zbb-valid.s
    A llvm/test/MC/RISCV/rv32zbbp-invalid.s
    A llvm/test/MC/RISCV/rv32zbbp-valid.s
    A llvm/test/MC/RISCV/rv32zbc-invalid.s
    A llvm/test/MC/RISCV/rv32zbc-valid.s
    A llvm/test/MC/RISCV/rv32zbe-invalid.s
    A llvm/test/MC/RISCV/rv32zbe-valid.s
    A llvm/test/MC/RISCV/rv32zbf-invalid.s
    A llvm/test/MC/RISCV/rv32zbf-valid.s
    A llvm/test/MC/RISCV/rv32zbp-invalid.s
    A llvm/test/MC/RISCV/rv32zbp-valid.s
    A llvm/test/MC/RISCV/rv32zbproposedc-invalid.s
    A llvm/test/MC/RISCV/rv32zbproposedc-valid.s
    A llvm/test/MC/RISCV/rv32zbr-invalid.s
    A llvm/test/MC/RISCV/rv32zbr-valid.s
    A llvm/test/MC/RISCV/rv32zbs-invalid.s
    A llvm/test/MC/RISCV/rv32zbs-valid.s
    A llvm/test/MC/RISCV/rv32zbt-invalid.s
    A llvm/test/MC/RISCV/rv32zbt-valid.s
    A llvm/test/MC/RISCV/rv64b-aliases-valid.s
    A llvm/test/MC/RISCV/rv64zbb-invalid.s
    A llvm/test/MC/RISCV/rv64zbb-valid.s
    A llvm/test/MC/RISCV/rv64zbbp-invalid.s
    A llvm/test/MC/RISCV/rv64zbbp-valid.s
    A llvm/test/MC/RISCV/rv64zbc-invalid.s
    A llvm/test/MC/RISCV/rv64zbc-valid.s
    A llvm/test/MC/RISCV/rv64zbe-invalid.s
    A llvm/test/MC/RISCV/rv64zbe-valid.s
    A llvm/test/MC/RISCV/rv64zbf-invalid.s
    A llvm/test/MC/RISCV/rv64zbf-valid.s
    A llvm/test/MC/RISCV/rv64zbm-invalid.s
    A llvm/test/MC/RISCV/rv64zbm-valid.s
    A llvm/test/MC/RISCV/rv64zbp-invalid.s
    A llvm/test/MC/RISCV/rv64zbp-valid.s
    A llvm/test/MC/RISCV/rv64zbproposedc-invalid.s
    A llvm/test/MC/RISCV/rv64zbproposedc-valid.s
    A llvm/test/MC/RISCV/rv64zbr-invalid.s
    A llvm/test/MC/RISCV/rv64zbr-valid.s
    A llvm/test/MC/RISCV/rv64zbs-invalid.s
    A llvm/test/MC/RISCV/rv64zbs-valid.s
    A llvm/test/MC/RISCV/rv64zbt-invalid.s
    A llvm/test/MC/RISCV/rv64zbt-valid.s

  Log Message:
  -----------
  [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)

This adds the instruction encoding and mnenomics for the proposed
RISC-V Bit Manipulation extension (version 0.92). It is implemented with
each category of instruction as its own target feature, with the 'b'
extension feature enabling all options. Since this extension is not yet
ratified, all target features are prefixed with 'experimental-' to note
their status.

Differential Revision: https://reviews.llvm.org/D65649


  Commit: dd1ee6dc076fe1da6cf6eeb9cf614d9c1796759a
      https://github.com/llvm/llvm-project/commit/dd1ee6dc076fe1da6cf6eeb9cf614d9c1796759a
  Author: Simon Cook <simon.cook at embecosm.com>
  Date:   2020-04-09 (Thu, 09 Apr 2020)

  Changed paths:
    M clang/include/clang/Driver/Options.td
    M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
    M clang/test/Driver/riscv-arch.c

  Log Message:
  -----------
  [RISCV] Support experimental/unratified extensions

This adds support for enabling experimental/unratified RISC-V ISA
extensions in the -march string in the case where an explicit version
number has been declared, and the -menable-experimental-extensions flag
has been provided.

This follows the design as discussed on the mailing lists in the
following RFC: http://lists.llvm.org/pipermail/llvm-dev/2020-January/138364.html

Since the RISC-V toolchain definition currently rejects any extension
with an explicit version number, the parsing logic has been tweaked to
support this, and to allow standard extensions to have their versions
checked in future patches.

The bitmanip 'b' extension has been added as a first use of this support,
it should easily extend to other as yet unratified extensions (such as
the vector 'v' extension).

Differential Revision: https://reviews.llvm.org/D73891


  Commit: 61ff29637501afcd7476e52064f7a266a95c6e28
      https://github.com/llvm/llvm-project/commit/61ff29637501afcd7476e52064f7a266a95c6e28
  Author: Scott Egerton <scott.egerton at embecosm.com>
  Date:   2020-04-09 (Thu, 09 Apr 2020)

  Changed paths:
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/lib/Basic/Targets/RISCV.h
    M clang/test/Preprocessor/riscv-target-features.c

  Log Message:
  -----------
  [RISCV] Add Clang frontend support for Bitmanip extension

This adds the __riscv_bitmanip macro and the 'b' target feature to enable it.

Differential Revision: https://reviews.llvm.org/D71553


Compare: https://github.com/llvm/llvm-project/compare/77b46fb326b5...61ff29637501