[all-commits] [llvm/llvm-project] 84aa58: CodeGen: Use Register in TargetLowering

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 84aa58cbe21696e2bbe56d50f045f44a7799171a
      https://github.com/llvm/llvm-project/commit/84aa58cbe21696e2bbe56d50f045f44a7799171a
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-04-08 (Wed, 08 Apr 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.h
    M llvm/lib/Target/Hexagon/HexagonISelLowering.h
    M llvm/lib/Target/Mips/MipsISelLowering.h
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/lib/Target/PowerPC/PPCISelLowering.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/Sparc/SparcISelLowering.h
    M llvm/lib/Target/SystemZ/SystemZISelLowering.h
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.h
    M llvm/lib/Target/XCore/XCoreISelLowering.h

  Log Message:
  -----------
  CodeGen: Use Register in TargetLowering


  Commit: ca0ace72987eb776f3103cf444bd160094a50cbc
      https://github.com/llvm/llvm-project/commit/ca0ace72987eb776f3103cf444bd160094a50cbc
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-04-08 (Wed, 08 Apr 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/LiveIntervals.h
    M llvm/include/llvm/CodeGen/MachineBasicBlock.h
    M llvm/lib/CodeGen/LiveIntervals.cpp
    M llvm/lib/CodeGen/MachineBasicBlock.cpp
    M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
    M llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp

  Log Message:
  -----------
  CodeGen: Use Register in MachineBasicBlock


  Commit: 7a46e36d518868fd77518c9e0dc13786ffb969c5
      https://github.com/llvm/llvm-project/commit/7a46e36d518868fd77518c9e0dc13786ffb969c5
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-04-08 (Wed, 08 Apr 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/CallingConvLower.h
    M llvm/lib/CodeGen/CallingConvLower.cpp

  Log Message:
  -----------
  CodeGen: Use Register more in CallLowering

Some of these MCPhysReg uses should probably be MCRegister, but right
now this would require more invasive changes.


  Commit: dcce3ef1d2a69d0f4162d1e85abcfc9c28d0152e
      https://github.com/llvm/llvm-project/commit/dcce3ef1d2a69d0f4162d1e85abcfc9c28d0152e
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-04-08 (Wed, 08 Apr 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/FastISel.h
    M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
    M llvm/lib/Target/X86/X86FastISel.cpp

  Log Message:
  -----------
  FastISel: Partially use Register

Doesn't try to convert the cases that depend on generated code.


Compare: https://github.com/llvm/llvm-project/compare/54502476e7bd...dcce3ef1d2a6