[all-commits] [llvm/llvm-project] c41685: [SelectionDAG] Make getZeroExtendInReg take a vect...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c41685b16fcceaa2078eb14eb27f6696f851eb49
      https://github.com/llvm/llvm-project/commit/c41685b16fcceaa2078eb14eb27f6696f851eb49
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-04-07 (Tue, 07 Apr 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp

  Log Message:
  -----------
  [SelectionDAG] Make getZeroExtendInReg take a vector VT if the operand VT is a vector.

This removes a call to getScalarType from a bunch of call sites.
It also makes the behavior consistent with SIGN_EXTEND_INREG.

Differential Revision: https://reviews.llvm.org/D77631