[all-commits] [llvm/llvm-project] a5d375: [AArch64] Allow logical immediates to have all-1 i...

[Fangrui Song via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: a5d375e0cbc4abf6e318270a1bc9c1c0961ae565
      https://github.com/llvm/llvm-project/commit/a5d375e0cbc4abf6e318270a1bc9c1c0961ae565
  Author: Fangrui Song <maskray at google.com>
  Date:   2020-04-06 (Mon, 06 Apr 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/test/MC/AArch64/SVE/mov-diagnostics.s
    M llvm/test/MC/AArch64/SVE/mov.s
    M llvm/test/MC/AArch64/arm64-logical-encoding.s

  Log Message:
  -----------
  [AArch64] Allow logical immediates to have all-1 in top bits

So that constant expressions like the following are permitted:

and w0, w0, #~(0xfe<<24)
and w1, w1, #~(0xff<<24)

The behavior matches GNU as (opcodes/aarch64-opc.c:aarch64_logical_immediate_p).

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D75885