[all-commits] [llvm/llvm-project] e5e719: [X86][SSE] lowerV8I16Shuffle - lower compaction sh...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: e5e719d8854a6bca60aff1d87f5b5eb556f55695
      https://github.com/llvm/llvm-project/commit/e5e719d8854a6bca60aff1d87f5b5eb556f55695
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-04-04 (Sat, 04 Apr 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/cast-vsel.ll
    M llvm/test/CodeGen/X86/masked_store_trunc.ll
    M llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
    M llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
    M llvm/test/CodeGen/X86/phaddsub.ll
    M llvm/test/CodeGen/X86/psubus.ll
    M llvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll
    M llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
    M llvm/test/CodeGen/X86/vector-reduce-and-bool.ll
    M llvm/test/CodeGen/X86/vector-reduce-or-bool.ll
    M llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
    M llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
    M llvm/test/CodeGen/X86/vector-trunc-packus.ll
    M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
    M llvm/test/CodeGen/X86/vector-trunc-usat.ll
    M llvm/test/CodeGen/X86/vector-trunc.ll

  Log Message:
  -----------
  [X86][SSE] lowerV8I16Shuffle - lower compaction shuffles using PACKUSDW(PBLENDW,PBLENDW) on SSE41+

Similar to the lowerV16I8Shuffle implementation, for binary compaction v8i16 shuffles we can avoid the PUNPCKLDQ(PSHUFB,PSHUFB) pattern on SSE41+ targets by using PACKUSDW and PBLENDW. Before SSE41 we would need to use PACKSSDW but that requires sign extension that seems to destroy any gains, even on targets without PSHUFB.

This is a bigger gain on AMD than Intel targets but should never be a regression, and avoiding the shuffle mask load(s) is always useful.

Noticed in codegen while dealing with PR31443.


  Commit: 87fd686f6fddc0f5cfb78934b01c32c3c8893443
      https://github.com/llvm/llvm-project/commit/87fd686f6fddc0f5cfb78934b01c32c3c8893443
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-04-04 (Sat, 04 Apr 2020)

  Changed paths:
    M llvm/test/Analysis/CostModel/X86/vector-extract.ll
    M llvm/test/Analysis/CostModel/X86/vector-insert.ll

  Log Message:
  -----------
  [CostModel][X86] Add insert/extract cost tests for sub-128bit vXi8/vXi16 vectors


  Commit: 6a57ba17c032807fcea04c622cce32f2c423610f
      https://github.com/llvm/llvm-project/commit/6a57ba17c032807fcea04c622cce32f2c423610f
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-04-04 (Sat, 04 Apr 2020)

  Changed paths:
    M llvm/test/Analysis/CostModel/X86/shuffle-broadcast.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-reverse.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-single-src.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-transpose.ll
    M llvm/test/Analysis/CostModel/X86/shuffle-two-src.ll

  Log Message:
  -----------
  [CostModel][X86] Add shuffle cost tests for sub-128bit vectors


Compare: https://github.com/llvm/llvm-project/compare/b90ea4f34194...6a57ba17c032