[all-commits] [llvm/llvm-project] 3c9064: [X86] Run XOP vector rotation tests with/without AVX2

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 3c9064ed963ebfc59e4164cbea0b932734785813
      https://github.com/llvm/llvm-project/commit/3c9064ed963ebfc59e4164cbea0b932734785813
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-04-01 (Wed, 01 Apr 2020)

  Changed paths:
    M llvm/test/CodeGen/X86/rotate_vec.ll

  Log Message:
  -----------
  [X86] Run XOP vector rotation tests with/without AVX2

I noticed this while reviewing D77152 - by only testing bdver4 we weren't checking an XOP target that only had AVX1


  Commit: f9f401dba179038591ad066bfa063cd5f3d5b4d8
      https://github.com/llvm/llvm-project/commit/f9f401dba179038591ad066bfa063cd5f3d5b4d8
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-04-01 (Wed, 01 Apr 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
    M llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
    M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll

  Log Message:
  -----------
  [X86][AVX] Add additional 256/512-bit test cases for PACKSS/PACKUS shuffle patterns

Also add lowerShuffleWithPACK call to lowerV32I16Shuffle - shuffle combining was catching it but we avoid a lot of temporary shuffle creations if we catch it at lowering first.


Compare: https://github.com/llvm/llvm-project/compare/72439b6b9557...f9f401dba179