[all-commits] [llvm/llvm-project] 9f7d41: [X86] Move combineLoopMAddPattern and combineLoopS...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 9f7d4150b9ec638a048c183c21a355195fdc4942
      https://github.com/llvm/llvm-project/commit/9f7d4150b9ec638a048c183c21a355195fdc4942
  Author: Craig Topper <craig.topper at gmail.com>
  Date:   2020-03-26 (Thu, 26 Mar 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
    M llvm/lib/Target/X86/CMakeLists.txt
    M llvm/lib/Target/X86/X86.h
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    A llvm/lib/Target/X86/X86PartialReduction.cpp
    M llvm/lib/Target/X86/X86TargetMachine.cpp
    R llvm/test/CodeGen/Generic/vector-redux.ll
    M llvm/test/CodeGen/X86/O3-pipeline.ll
    M llvm/test/CodeGen/X86/madd.ll
    M llvm/test/CodeGen/X86/min-legal-vector-width.ll
    M llvm/test/CodeGen/X86/sad.ll

  Log Message:
  -----------
  [X86] Move combineLoopMAddPattern and combineLoopSADPattern to an IR pass before SelecitonDAG.

These transforms rely on a vector reduction flag on the SDNode
set by SelectionDAGBuilder. This flag exists because SelectionDAG
can't see across basic blocks so SelectionDAGBuilder is looking
across and saving the info. X86 is the only target that uses this
flag currently. By removing the X86 code we can remove the flag
and the SelectionDAGBuilder code.

This pass adds a dedicated IR pass for X86 that looks across the
blocks and transforms the IR into a form that the X86 SelectionDAG
can finish.

An advantage of this new approach is that we can enhance it to
shrink the phi nodes and final reduction tree based on the zeroes
that we need to concatenate to bring the partially reduced
reduction back up to the original width.

Differential Revision: https://reviews.llvm.org/D76649