[all-commits] [llvm/llvm-project] 1ef7bf: [PowerPC] Improve the way legalize mul for v8i16 a...

[QingShan Zhang via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 1ef7bf412141811fa80473e0f13e9dc76972b1a0
      https://github.com/llvm/llvm-project/commit/1ef7bf412141811fa80473e0f13e9dc76972b1a0
  Author: QingShan Zhang <qshanz at cn.ibm.com>
  Date:   2020-03-26 (Thu, 26 Mar 2020)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/lib/Target/PowerPC/PPCInstrAltivec.td
    M llvm/test/CodeGen/PowerPC/vmladduhm.ll

  Log Message:
  -----------
  [PowerPC] Improve the way legalize mul for v8i16 and add pattern to match mul + add

We can legalize the operation MUL for v8i16 with instruction (vmladduhm A, B, 0)
if altivec enabled. Now, it is set as custom and expand it later, which is not
the right way. And then, we can add the pattern to match the mul + add with (vmladduhm A, B, C)

Reviewed By: Nemanjai

Differential Revision: https://reviews.llvm.org/D76751