[all-commits] [llvm/llvm-project] 94cace: [ARM][LowOverheadLoops] Add checks for narrowing

[Sam Parker via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 94cacebccadf1e0821bdab6983d9f5251f73eab0
      https://github.com/llvm/llvm-project/commit/94cacebccadf1e0821bdab6983d9f5251f73eab0
  Author: Sam Parker <sam.parker at arm.com>
  Date:   2020-03-24 (Tue, 24 Mar 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

  Log Message:
  -----------
  [ARM][LowOverheadLoops] Add checks for narrowing

Modify ValidateLiveOuts to track 'FalseLaneZeros' more precisely,
including checks on specific operations that can generate non-zeros
from zero values, e.g VMVN. We can then check that any instructions
that retain some information in their output register (all narrowing
instructions) that they only use and def registers that always have
zeros in their falsely predicated bytes, whether or not tail
predication happens.

Most of the logic remains the same, just the names of the data
structures and helpers have been renamed to reflect the change in
logic. The key change, apart from the opcode checkers, is that the
FalseZeros set now strictly contains only instructions which will
always generate zeros, and not instructions that could also have
their false bytes masked away later.

Differential Revision: https://reviews.llvm.org/D76235