[all-commits] [llvm/llvm-project] c5fd9e: [DAG] Don't permit EXTLOAD when combining FSHL/FSH...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c5fd9e3888d5e8f849a872949b5891f6ea2eba56
      https://github.com/llvm/llvm-project/commit/c5fd9e3888d5e8f849a872949b5891f6ea2eba56
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-03-21 (Sat, 21 Mar 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/X86/funnel-shift.ll

  Log Message:
  -----------
  [DAG] Don't permit EXTLOAD when combining FSHL/FSHR consecutive loads (PR45265)

Technically we can permit EXTLOAD of the LHS operand but only if all the extended bits are shifted out. Until we test coverage for that case, I'm just disabling this to fix PR45265.