[all-commits] [llvm/llvm-project] b3499f: [ARM] Change VDUP type to i32 for MVE

[David Green via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: b3499f572d37ce238c3f78668ef7e885d357745d
      https://github.com/llvm/llvm-project/commit/b3499f572d37ce238c3f78668ef7e885d357745d
  Author: David Green <david.green at arm.com>
  Date:   2020-03-20 (Fri, 20 Mar 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMInstrMVE.td
    M llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
    M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
    M llvm/test/CodeGen/Thumb2/mve-fmas.ll
    M llvm/test/CodeGen/Thumb2/mve-intrinsics/dup.ll
    M llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll
    M llvm/test/CodeGen/Thumb2/mve-intrinsics/vaddq.ll
    M llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulq.ll
    M llvm/test/CodeGen/Thumb2/mve-intrinsics/vsubq.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll
    M llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
    M llvm/test/CodeGen/Thumb2/mve-vdup.ll
    M llvm/test/CodeGen/Thumb2/mve-vldst4.ll

  Log Message:
  -----------
  [ARM] Change VDUP type to i32 for MVE

The MVE VDUP instruction take a GPR and splats into every lane of a
vector register. Unlike NEON we do not have a VDUPLANE equivalent
instruction, doing the same splat from a fp register. Previously a VDUP
to a v4f32/v8f16 would be represented as a (v4f32 VDUP f32), which
would mean the instruction pattern needs to add a COPY_TO_REGCLASS to
the GPR.

Instead this now converts that earlier during an ISel DAG combine,
converting (VDUP x) to (VDUP (bitcast x)). This can allow instruction
selection to tell that the input needs to be an i32, which in one of the
testcases allows it to use ldr (or specifically ldm) over (vldr;vmov).

Whilst being simple enough for floats, as the types sizes are the same,
these is no BITCAST equivalent for getting a half into a i32. This uses
a VMOVrh ARMISD node, which doesn't know the same tricks yet.

Differential Revision: https://reviews.llvm.org/D76292