[all-commits] [llvm/llvm-project] e225e7: [TableGen][GlobalISel] Rework RegisterBankEmitter ...

[lewis-revill via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: e225e770f7e94cc1b6e2fababcc7b238db65cfee
      https://github.com/llvm/llvm-project/commit/e225e770f7e94cc1b6e2fababcc7b238db65cfee
  Author: lewis-revill <lewis.revill at embecosm.com>
  Date:   2020-03-18 (Wed, 18 Mar 2020)

  Changed paths:
    M llvm/utils/TableGen/CodeGenRegisters.cpp
    M llvm/utils/TableGen/CodeGenRegisters.h
    M llvm/utils/TableGen/RegisterBankEmitter.cpp

  Log Message:
  -----------
  [TableGen][GlobalISel] Rework RegisterBankEmitter for easier const correctness.

This patch rewrites the RegisterBankEmitter class to derive
RegisterClassHierarchy from CodeGenTarget::getRegBank() rather than
constructing our own copy. All are now accessed through a const
reference.

Differential Revision: https://reviews.llvm.org/D76006


  Commit: e9f22fd4293a65bcdcf1b18b91c72f63e5e9e45b
      https://github.com/llvm/llvm-project/commit/e9f22fd4293a65bcdcf1b18b91c72f63e5e9e45b
  Author: lewis-revill <lewis.revill at embecosm.com>
  Date:   2020-03-18 (Wed, 18 Mar 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/RegisterBank.h
    M llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
    M llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp
    M llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h
    M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
    M llvm/utils/TableGen/RegisterBankEmitter.cpp

  Log Message:
  -----------
  [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes

This patch generates TableGen descriptions for the specified register
banks which contain a list of register sizes corresponding to the
available HwModes. The appropriate size is used during codegen according
to the current HwMode. As this HwMode was not available on generation,
it is set upon construction of the RegisterBankInfo class. Targets
simply need to provide the HwMode argument to the
<target>GenRegisterBankInfo constructor.

The RISC-V RegisterBankInfo constructor has been updated accordingly
(plus an unused argument removed).

Differential Revision: https://reviews.llvm.org/D76007


Compare: https://github.com/llvm/llvm-project/compare/4e8830830ee4...e9f22fd4293a