[all-commits] [llvm/llvm-project] 314542: [mlir][NFC] Replace all usages of PatternMatchResu...
River Riddle via All-commits
all-commits at lists.llvm.org
Tue Mar 17 20:23:15 PDT 2020
Branch: refs/heads/master
Home: https://github.com/llvm/llvm-project
Commit: 3145427dd73f0ee16dac4044890e2e2d2cae5040
https://github.com/llvm/llvm-project/commit/3145427dd73f0ee16dac4044890e2e2d2cae5040
Author: River Riddle <riddleriver at gmail.com>
Date: 2020-03-17 (Tue, 17 Mar 2020)
Changed paths:
M mlir/docs/DialectConversion.md
M mlir/docs/QuickstartRewrites.md
M mlir/docs/Tutorials/Toy/Ch-3.md
M mlir/docs/Tutorials/Toy/Ch-5.md
M mlir/examples/toy/Ch3/mlir/ToyCombine.cpp
M mlir/examples/toy/Ch4/mlir/ToyCombine.cpp
M mlir/examples/toy/Ch5/mlir/LowerToAffineLoops.cpp
M mlir/examples/toy/Ch5/mlir/ToyCombine.cpp
M mlir/examples/toy/Ch6/mlir/LowerToAffineLoops.cpp
M mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp
M mlir/examples/toy/Ch6/mlir/ToyCombine.cpp
M mlir/examples/toy/Ch7/mlir/LowerToAffineLoops.cpp
M mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp
M mlir/examples/toy/Ch7/mlir/ToyCombine.cpp
M mlir/include/mlir/Dialect/Linalg/Transforms/LinalgTransformPatterns.td
M mlir/include/mlir/IR/PatternMatch.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
M mlir/lib/Conversion/GPUCommon/IndexIntrinsicsOpLowering.h
M mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp
M mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp
M mlir/lib/Conversion/LinalgToSPIRV/LinalgToSPIRV.cpp
M mlir/lib/Conversion/LoopToStandard/ConvertLoopToStandard.cpp
M mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp
M mlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp
M mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp
M mlir/lib/Conversion/StandardToSPIRV/LegalizeStandardForSPIRV.cpp
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/lib/Conversion/VectorToLoops/ConvertVectorToLoops.cpp
M mlir/lib/Dialect/AffineOps/AffineOps.cpp
M mlir/lib/Dialect/FxpMathOps/Transforms/LowerUniformRealMath.cpp
M mlir/lib/Dialect/GPU/Transforms/AllReduceLowering.cpp
M mlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
M mlir/lib/Dialect/Linalg/Transforms/LinalgToLoops.cpp
M mlir/lib/Dialect/Quant/Transforms/ConvertConst.cpp
M mlir/lib/Dialect/Quant/Transforms/ConvertSimQuant.cpp
M mlir/lib/Dialect/SPIRV/SPIRVCanonicalization.cpp
M mlir/lib/Dialect/SPIRV/SPIRVLowering.cpp
M mlir/lib/Dialect/SPIRV/Transforms/DecorateSPIRVCompositeTypeLayoutPass.cpp
M mlir/lib/Dialect/SPIRV/Transforms/LowerABIAttributesPass.cpp
M mlir/lib/Dialect/StandardOps/IR/Ops.cpp
M mlir/lib/Dialect/Vector/VectorOps.cpp
M mlir/lib/Dialect/Vector/VectorTransforms.cpp
M mlir/lib/IR/PatternMatch.cpp
M mlir/lib/Quantizer/Transforms/RemoveInstrumentationPass.cpp
M mlir/lib/Transforms/DialectConversion.cpp
M mlir/test/lib/Dialect/SPIRV/TestAvailability.cpp
M mlir/test/lib/TestDialect/TestDialect.cpp
M mlir/test/lib/TestDialect/TestPatterns.cpp
M mlir/tools/mlir-tblgen/RewriterGen.cpp
Log Message:
-----------
[mlir][NFC] Replace all usages of PatternMatchResult with LogicalResult
This also replaces usages of matchSuccess/matchFailure with success/failure respectively.
Differential Revision: https://reviews.llvm.org/D76313
Commit: bd0ca2627cfa1acde2a272347ed55d88a9751869
https://github.com/llvm/llvm-project/commit/bd0ca2627cfa1acde2a272347ed55d88a9751869
Author: River Riddle <riddleriver at gmail.com>
Date: 2020-03-17 (Tue, 17 Mar 2020)
Changed paths:
M mlir/tools/mlir-tblgen/RewriterGen.cpp
Log Message:
-----------
[mlir] Update DRR patterns to notify the rewriter why a pattern fails to match.
Summary:
This adds support in RewriterGen for calling into the new `PatternRewriter::notifyMatchFailure` hook. This lets derived pattern rewriters display this information to users, an example from DialectConversion is shown below:
```
Legalizing operation : 'std.and'(0x60e0000066a0) {
* Fold {
} -> FAILURE : unable to fold
* Pattern : 'std.and -> (spv.BitwiseAnd)' {
** Failure : operand 0 of op 'std.and' failed to satisfy constraint: '8/16/32/64-bit integer or vector of 8/16/32/64-bit integer values of length 2/3/4'
} -> FAILURE : pattern failed to match
* Pattern : 'std.and -> (spv.LogicalAnd)' {
** Failure : operand 0 of op 'std.and' failed to satisfy constraint: 'bool or vector of bool values of length 2/3/4'
} -> FAILURE : pattern failed to match
} -> FAILURE : no matched legalization pattern
```
Differential Revision: https://reviews.llvm.org/D76335
Compare: https://github.com/llvm/llvm-project/compare/2fae7878d552...bd0ca2627cfa
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