[all-commits] [llvm/llvm-project] d9a012: AMDGPU/GlobalISel: Adjust image load register type...

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: d9a012ed8a5a12be0c96fe325aec893c7fc6d288
      https://github.com/llvm/llvm-project/commit/d9a012ed8a5a12be0c96fe325aec893c7fc6d288
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll

  Log Message:
  -----------
  AMDGPU/GlobalISel: Adjust image load register type based on dmask

Trim elements that won't be written. The equivalent still needs to be
done for writes. Also start widening 3 elements to 4
elements. Selection will get the count from the dmask.