[all-commits] [llvm/llvm-project] 2b3b45: [TargetLowering] Only demand a funnelshift's modul...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 2b3b453a827b2867b38b47acd17edafa314c9d7e
      https://github.com/llvm/llvm-project/commit/2b3b453a827b2867b38b47acd17edafa314c9d7e
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-03-16 (Mon, 16 Mar 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AMDGPU/fshl.ll
    M llvm/test/CodeGen/X86/shift-by-signext.ll

  Log Message:
  -----------
  [TargetLowering] Only demand a funnelshift's modulo amount bits

ISD::FSHL/FSHR shift amount values are guaranteed to act as a modulo amount, so for power-of-2 bitwidths we only need the lowest bits.