[all-commits] [llvm/llvm-project] ecd6d7: [test] llvm/test/: change llvm-objdump single-dash...
Fangrui Song via All-commits
all-commits at lists.llvm.org
Sun Mar 15 17:46:34 PDT 2020
Branch: refs/heads/master
Home: https://github.com/llvm/llvm-project
Commit: ecd6d7254e6452bd4663a473f46bd13bcf2bfeec
https://github.com/llvm/llvm-project/commit/ecd6d7254e6452bd4663a473f46bd13bcf2bfeec
Author: Fangrui Song <maskray at google.com>
Date: 2020-03-15 (Sun, 15 Mar 2020)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-elf-calls.ll
M llvm/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll
M llvm/test/CodeGen/AArch64/arm64_32.ll
M llvm/test/CodeGen/AArch64/bitfield-insert-0.ll
M llvm/test/CodeGen/AArch64/callbr-asm-obj-file.ll
M llvm/test/CodeGen/AArch64/inlineasm-ldr-pseudo.ll
M llvm/test/CodeGen/AArch64/simple-macho.ll
M llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir
M llvm/test/CodeGen/AMDGPU/call-encoding.ll
M llvm/test/CodeGen/AMDGPU/nop-data.ll
M llvm/test/CodeGen/AMDGPU/s_code_end.ll
M llvm/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll
M llvm/test/CodeGen/ARM/Windows/division-range.ll
M llvm/test/CodeGen/ARM/inlineasm-switch-mode-oneway-from-arm.ll
M llvm/test/CodeGen/ARM/inlineasm-switch-mode-oneway-from-thumb.ll
M llvm/test/CodeGen/ARM/krait-cpu-div-attribute.ll
M llvm/test/CodeGen/ARM/local-call.ll
M llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll
M llvm/test/CodeGen/ARM/thumb1-varalloc.ll
M llvm/test/CodeGen/ARM/trap.ll
M llvm/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll
M llvm/test/CodeGen/BPF/objdump_imm_hex.ll
M llvm/test/CodeGen/Hexagon/bug18008.ll
M llvm/test/CodeGen/Hexagon/vect-regpairs.ll
M llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll
M llvm/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll
M llvm/test/CodeGen/Mips/micromips-atomic1.ll
M llvm/test/CodeGen/Mips/micromips-eva.mir
M llvm/test/CodeGen/Mips/tailcall/tailcall-wrong-isa.ll
M llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir
M llvm/test/CodeGen/PowerPC/2016-04-28-setjmp.ll
M llvm/test/CodeGen/PowerPC/alignlongjumptest.mir
M llvm/test/CodeGen/RISCV/compress-float.ll
M llvm/test/CodeGen/RISCV/compress-inline-asm.ll
M llvm/test/CodeGen/RISCV/compress.ll
M llvm/test/CodeGen/RISCV/option-norvc.ll
M llvm/test/CodeGen/RISCV/option-rvc.ll
M llvm/test/CodeGen/Thumb/large-stack.ll
M llvm/test/CodeGen/X86/2014-08-29-CompactUnwind.ll
M llvm/test/CodeGen/X86/callbr-asm-obj-file.ll
M llvm/test/CodeGen/X86/compact-unwind.ll
M llvm/test/CodeGen/X86/implicit-faultmap.ll
M llvm/test/CodeGen/X86/mingw-comdats-xdata.ll
M llvm/test/CodeGen/X86/mingw-comdats.ll
M llvm/test/CodeGen/X86/patchable-prologue.ll
M llvm/test/CodeGen/X86/xray-section-group.ll
M llvm/test/DebugInfo/COFF/no-cus.ll
M llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll
M llvm/test/DebugInfo/X86/DW_AT_location-reference.ll
M llvm/test/MC/AArch64/SVE/abs.s
M llvm/test/MC/AArch64/SVE/add.s
M llvm/test/MC/AArch64/SVE/addpl.s
M llvm/test/MC/AArch64/SVE/addvl.s
M llvm/test/MC/AArch64/SVE/adr.s
M llvm/test/MC/AArch64/SVE/and.s
M llvm/test/MC/AArch64/SVE/ands.s
M llvm/test/MC/AArch64/SVE/andv.s
M llvm/test/MC/AArch64/SVE/asr.s
M llvm/test/MC/AArch64/SVE/asrd.s
M llvm/test/MC/AArch64/SVE/asrr.s
M llvm/test/MC/AArch64/SVE/bic.s
M llvm/test/MC/AArch64/SVE/bics.s
M llvm/test/MC/AArch64/SVE/brka.s
M llvm/test/MC/AArch64/SVE/brkas.s
M llvm/test/MC/AArch64/SVE/brkb.s
M llvm/test/MC/AArch64/SVE/brkbs.s
M llvm/test/MC/AArch64/SVE/brkn.s
M llvm/test/MC/AArch64/SVE/brkns.s
M llvm/test/MC/AArch64/SVE/brkpa.s
M llvm/test/MC/AArch64/SVE/brkpas.s
M llvm/test/MC/AArch64/SVE/brkpb.s
M llvm/test/MC/AArch64/SVE/brkpbs.s
M llvm/test/MC/AArch64/SVE/clasta.s
M llvm/test/MC/AArch64/SVE/clastb.s
M llvm/test/MC/AArch64/SVE/cls.s
M llvm/test/MC/AArch64/SVE/clz.s
M llvm/test/MC/AArch64/SVE/cmpeq.s
M llvm/test/MC/AArch64/SVE/cmpge.s
M llvm/test/MC/AArch64/SVE/cmpgt.s
M llvm/test/MC/AArch64/SVE/cmphi.s
M llvm/test/MC/AArch64/SVE/cmphs.s
M llvm/test/MC/AArch64/SVE/cmple.s
M llvm/test/MC/AArch64/SVE/cmplo.s
M llvm/test/MC/AArch64/SVE/cmpls.s
M llvm/test/MC/AArch64/SVE/cmplt.s
M llvm/test/MC/AArch64/SVE/cmpne.s
M llvm/test/MC/AArch64/SVE/cnot.s
M llvm/test/MC/AArch64/SVE/cnt.s
M llvm/test/MC/AArch64/SVE/cntb.s
M llvm/test/MC/AArch64/SVE/cntd.s
M llvm/test/MC/AArch64/SVE/cnth.s
M llvm/test/MC/AArch64/SVE/cntp.s
M llvm/test/MC/AArch64/SVE/cntw.s
M llvm/test/MC/AArch64/SVE/compact.s
M llvm/test/MC/AArch64/SVE/cpy.s
M llvm/test/MC/AArch64/SVE/ctermeq.s
M llvm/test/MC/AArch64/SVE/ctermne.s
M llvm/test/MC/AArch64/SVE/decb.s
M llvm/test/MC/AArch64/SVE/decd.s
M llvm/test/MC/AArch64/SVE/dech.s
M llvm/test/MC/AArch64/SVE/decp.s
M llvm/test/MC/AArch64/SVE/decw.s
M llvm/test/MC/AArch64/SVE/dup.s
M llvm/test/MC/AArch64/SVE/dupm.s
M llvm/test/MC/AArch64/SVE/eon.s
M llvm/test/MC/AArch64/SVE/eor.s
M llvm/test/MC/AArch64/SVE/eors.s
M llvm/test/MC/AArch64/SVE/eorv.s
M llvm/test/MC/AArch64/SVE/ext.s
M llvm/test/MC/AArch64/SVE/fabd.s
M llvm/test/MC/AArch64/SVE/fabs.s
M llvm/test/MC/AArch64/SVE/facge.s
M llvm/test/MC/AArch64/SVE/facgt.s
M llvm/test/MC/AArch64/SVE/facle.s
M llvm/test/MC/AArch64/SVE/faclt.s
M llvm/test/MC/AArch64/SVE/fadd.s
M llvm/test/MC/AArch64/SVE/fadda.s
M llvm/test/MC/AArch64/SVE/faddv.s
M llvm/test/MC/AArch64/SVE/fcadd.s
M llvm/test/MC/AArch64/SVE/fcmeq.s
M llvm/test/MC/AArch64/SVE/fcmge.s
M llvm/test/MC/AArch64/SVE/fcmgt.s
M llvm/test/MC/AArch64/SVE/fcmla.s
M llvm/test/MC/AArch64/SVE/fcmle.s
M llvm/test/MC/AArch64/SVE/fcmlt.s
M llvm/test/MC/AArch64/SVE/fcmne.s
M llvm/test/MC/AArch64/SVE/fcmuo.s
M llvm/test/MC/AArch64/SVE/fcpy.s
M llvm/test/MC/AArch64/SVE/fcvt.s
M llvm/test/MC/AArch64/SVE/fcvtzs.s
M llvm/test/MC/AArch64/SVE/fcvtzu.s
M llvm/test/MC/AArch64/SVE/fdiv.s
M llvm/test/MC/AArch64/SVE/fdivr.s
M llvm/test/MC/AArch64/SVE/fdup.s
M llvm/test/MC/AArch64/SVE/fexpa.s
M llvm/test/MC/AArch64/SVE/fmad.s
M llvm/test/MC/AArch64/SVE/fmax.s
M llvm/test/MC/AArch64/SVE/fmaxnm.s
M llvm/test/MC/AArch64/SVE/fmaxnmv.s
M llvm/test/MC/AArch64/SVE/fmaxv.s
M llvm/test/MC/AArch64/SVE/fmin.s
M llvm/test/MC/AArch64/SVE/fminnm.s
M llvm/test/MC/AArch64/SVE/fminnmv.s
M llvm/test/MC/AArch64/SVE/fminv.s
M llvm/test/MC/AArch64/SVE/fmla.s
M llvm/test/MC/AArch64/SVE/fmls.s
M llvm/test/MC/AArch64/SVE/fmov.s
M llvm/test/MC/AArch64/SVE/fmsb.s
M llvm/test/MC/AArch64/SVE/fmul.s
M llvm/test/MC/AArch64/SVE/fmulx.s
M llvm/test/MC/AArch64/SVE/fneg.s
M llvm/test/MC/AArch64/SVE/fnmad.s
M llvm/test/MC/AArch64/SVE/fnmla.s
M llvm/test/MC/AArch64/SVE/fnmls.s
M llvm/test/MC/AArch64/SVE/fnmsb.s
M llvm/test/MC/AArch64/SVE/frecpe.s
M llvm/test/MC/AArch64/SVE/frecps.s
M llvm/test/MC/AArch64/SVE/frecpx.s
M llvm/test/MC/AArch64/SVE/frinta.s
M llvm/test/MC/AArch64/SVE/frinti.s
M llvm/test/MC/AArch64/SVE/frintm.s
M llvm/test/MC/AArch64/SVE/frintn.s
M llvm/test/MC/AArch64/SVE/frintp.s
M llvm/test/MC/AArch64/SVE/frintx.s
M llvm/test/MC/AArch64/SVE/frintz.s
M llvm/test/MC/AArch64/SVE/frsqrte.s
M llvm/test/MC/AArch64/SVE/frsqrts.s
M llvm/test/MC/AArch64/SVE/fscale.s
M llvm/test/MC/AArch64/SVE/fsqrt.s
M llvm/test/MC/AArch64/SVE/fsub.s
M llvm/test/MC/AArch64/SVE/fsubr.s
M llvm/test/MC/AArch64/SVE/ftmad.s
M llvm/test/MC/AArch64/SVE/ftsmul.s
M llvm/test/MC/AArch64/SVE/ftssel.s
M llvm/test/MC/AArch64/SVE/incb.s
M llvm/test/MC/AArch64/SVE/incd.s
M llvm/test/MC/AArch64/SVE/inch.s
M llvm/test/MC/AArch64/SVE/incp.s
M llvm/test/MC/AArch64/SVE/incw.s
M llvm/test/MC/AArch64/SVE/index.s
M llvm/test/MC/AArch64/SVE/insr.s
M llvm/test/MC/AArch64/SVE/lasta.s
M llvm/test/MC/AArch64/SVE/lastb.s
M llvm/test/MC/AArch64/SVE/ld1b.s
M llvm/test/MC/AArch64/SVE/ld1d.s
M llvm/test/MC/AArch64/SVE/ld1h.s
M llvm/test/MC/AArch64/SVE/ld1rb.s
M llvm/test/MC/AArch64/SVE/ld1rd.s
M llvm/test/MC/AArch64/SVE/ld1rh.s
M llvm/test/MC/AArch64/SVE/ld1rqb.s
M llvm/test/MC/AArch64/SVE/ld1rqd.s
M llvm/test/MC/AArch64/SVE/ld1rqh.s
M llvm/test/MC/AArch64/SVE/ld1rqw.s
M llvm/test/MC/AArch64/SVE/ld1rsb.s
M llvm/test/MC/AArch64/SVE/ld1rsh.s
M llvm/test/MC/AArch64/SVE/ld1rsw.s
M llvm/test/MC/AArch64/SVE/ld1rw.s
M llvm/test/MC/AArch64/SVE/ld1sb.s
M llvm/test/MC/AArch64/SVE/ld1sh.s
M llvm/test/MC/AArch64/SVE/ld1sw.s
M llvm/test/MC/AArch64/SVE/ld1w.s
M llvm/test/MC/AArch64/SVE/ld2b.s
M llvm/test/MC/AArch64/SVE/ld2d.s
M llvm/test/MC/AArch64/SVE/ld2h.s
M llvm/test/MC/AArch64/SVE/ld2w.s
M llvm/test/MC/AArch64/SVE/ld3b.s
M llvm/test/MC/AArch64/SVE/ld3d.s
M llvm/test/MC/AArch64/SVE/ld3h.s
M llvm/test/MC/AArch64/SVE/ld3w.s
M llvm/test/MC/AArch64/SVE/ld4b.s
M llvm/test/MC/AArch64/SVE/ld4d.s
M llvm/test/MC/AArch64/SVE/ld4h.s
M llvm/test/MC/AArch64/SVE/ld4w.s
M llvm/test/MC/AArch64/SVE/ldff1b.s
M llvm/test/MC/AArch64/SVE/ldff1d.s
M llvm/test/MC/AArch64/SVE/ldff1h.s
M llvm/test/MC/AArch64/SVE/ldff1sb.s
M llvm/test/MC/AArch64/SVE/ldff1sh.s
M llvm/test/MC/AArch64/SVE/ldff1sw.s
M llvm/test/MC/AArch64/SVE/ldff1w.s
M llvm/test/MC/AArch64/SVE/ldnf1b.s
M llvm/test/MC/AArch64/SVE/ldnf1d.s
M llvm/test/MC/AArch64/SVE/ldnf1h.s
M llvm/test/MC/AArch64/SVE/ldnf1sb.s
M llvm/test/MC/AArch64/SVE/ldnf1sh.s
M llvm/test/MC/AArch64/SVE/ldnf1sw.s
M llvm/test/MC/AArch64/SVE/ldnf1w.s
M llvm/test/MC/AArch64/SVE/ldnt1b.s
M llvm/test/MC/AArch64/SVE/ldnt1d.s
M llvm/test/MC/AArch64/SVE/ldnt1h.s
M llvm/test/MC/AArch64/SVE/ldnt1w.s
M llvm/test/MC/AArch64/SVE/ldr.s
M llvm/test/MC/AArch64/SVE/lsl.s
M llvm/test/MC/AArch64/SVE/lslr.s
M llvm/test/MC/AArch64/SVE/lsr.s
M llvm/test/MC/AArch64/SVE/lsrr.s
M llvm/test/MC/AArch64/SVE/mad.s
M llvm/test/MC/AArch64/SVE/mla.s
M llvm/test/MC/AArch64/SVE/mls.s
M llvm/test/MC/AArch64/SVE/mov.s
M llvm/test/MC/AArch64/SVE/movprfx.s
M llvm/test/MC/AArch64/SVE/movs.s
M llvm/test/MC/AArch64/SVE/msb.s
M llvm/test/MC/AArch64/SVE/mul.s
M llvm/test/MC/AArch64/SVE/nand.s
M llvm/test/MC/AArch64/SVE/nands.s
M llvm/test/MC/AArch64/SVE/neg.s
M llvm/test/MC/AArch64/SVE/nor.s
M llvm/test/MC/AArch64/SVE/nors.s
M llvm/test/MC/AArch64/SVE/not.s
M llvm/test/MC/AArch64/SVE/nots.s
M llvm/test/MC/AArch64/SVE/orn.s
M llvm/test/MC/AArch64/SVE/orns.s
M llvm/test/MC/AArch64/SVE/orr.s
M llvm/test/MC/AArch64/SVE/orrs.s
M llvm/test/MC/AArch64/SVE/orv.s
M llvm/test/MC/AArch64/SVE/pfalse.s
M llvm/test/MC/AArch64/SVE/pfirst.s
M llvm/test/MC/AArch64/SVE/pnext.s
M llvm/test/MC/AArch64/SVE/prfb.s
M llvm/test/MC/AArch64/SVE/prfd.s
M llvm/test/MC/AArch64/SVE/prfh.s
M llvm/test/MC/AArch64/SVE/prfw.s
M llvm/test/MC/AArch64/SVE/ptest.s
M llvm/test/MC/AArch64/SVE/ptrue.s
M llvm/test/MC/AArch64/SVE/ptrues.s
M llvm/test/MC/AArch64/SVE/punpkhi.s
M llvm/test/MC/AArch64/SVE/punpklo.s
M llvm/test/MC/AArch64/SVE/rbit.s
M llvm/test/MC/AArch64/SVE/rdffr.s
M llvm/test/MC/AArch64/SVE/rdffrs.s
M llvm/test/MC/AArch64/SVE/rdvl.s
M llvm/test/MC/AArch64/SVE/rev.s
M llvm/test/MC/AArch64/SVE/revb.s
M llvm/test/MC/AArch64/SVE/revh.s
M llvm/test/MC/AArch64/SVE/revw.s
M llvm/test/MC/AArch64/SVE/sabd.s
M llvm/test/MC/AArch64/SVE/saddv.s
M llvm/test/MC/AArch64/SVE/scvtf.s
M llvm/test/MC/AArch64/SVE/sdiv.s
M llvm/test/MC/AArch64/SVE/sdivr.s
M llvm/test/MC/AArch64/SVE/sdot.s
M llvm/test/MC/AArch64/SVE/sel.s
M llvm/test/MC/AArch64/SVE/setffr.s
M llvm/test/MC/AArch64/SVE/smax.s
M llvm/test/MC/AArch64/SVE/smaxv.s
M llvm/test/MC/AArch64/SVE/smin.s
M llvm/test/MC/AArch64/SVE/sminv.s
M llvm/test/MC/AArch64/SVE/smulh.s
M llvm/test/MC/AArch64/SVE/splice.s
M llvm/test/MC/AArch64/SVE/sqadd.s
M llvm/test/MC/AArch64/SVE/sqdecb.s
M llvm/test/MC/AArch64/SVE/sqdecd.s
M llvm/test/MC/AArch64/SVE/sqdech.s
M llvm/test/MC/AArch64/SVE/sqdecp.s
M llvm/test/MC/AArch64/SVE/sqdecw.s
M llvm/test/MC/AArch64/SVE/sqincb.s
M llvm/test/MC/AArch64/SVE/sqincd.s
M llvm/test/MC/AArch64/SVE/sqinch.s
M llvm/test/MC/AArch64/SVE/sqincp.s
M llvm/test/MC/AArch64/SVE/sqincw.s
M llvm/test/MC/AArch64/SVE/sqsub.s
M llvm/test/MC/AArch64/SVE/st1b.s
M llvm/test/MC/AArch64/SVE/st1d.s
M llvm/test/MC/AArch64/SVE/st1h.s
M llvm/test/MC/AArch64/SVE/st1w.s
M llvm/test/MC/AArch64/SVE/st2b.s
M llvm/test/MC/AArch64/SVE/st2d.s
M llvm/test/MC/AArch64/SVE/st2h.s
M llvm/test/MC/AArch64/SVE/st2w.s
M llvm/test/MC/AArch64/SVE/st3b.s
M llvm/test/MC/AArch64/SVE/st3d.s
M llvm/test/MC/AArch64/SVE/st3h.s
M llvm/test/MC/AArch64/SVE/st3w.s
M llvm/test/MC/AArch64/SVE/st4b.s
M llvm/test/MC/AArch64/SVE/st4d.s
M llvm/test/MC/AArch64/SVE/st4h.s
M llvm/test/MC/AArch64/SVE/st4w.s
M llvm/test/MC/AArch64/SVE/stnt1b.s
M llvm/test/MC/AArch64/SVE/stnt1d.s
M llvm/test/MC/AArch64/SVE/stnt1h.s
M llvm/test/MC/AArch64/SVE/stnt1w.s
M llvm/test/MC/AArch64/SVE/str.s
M llvm/test/MC/AArch64/SVE/sub.s
M llvm/test/MC/AArch64/SVE/subr.s
M llvm/test/MC/AArch64/SVE/sunpkhi.s
M llvm/test/MC/AArch64/SVE/sunpklo.s
M llvm/test/MC/AArch64/SVE/sxtb.s
M llvm/test/MC/AArch64/SVE/sxth.s
M llvm/test/MC/AArch64/SVE/sxtw.s
M llvm/test/MC/AArch64/SVE/system-regs.s
M llvm/test/MC/AArch64/SVE/tbl.s
M llvm/test/MC/AArch64/SVE/trn1.s
M llvm/test/MC/AArch64/SVE/trn2.s
M llvm/test/MC/AArch64/SVE/uabd.s
M llvm/test/MC/AArch64/SVE/uaddv.s
M llvm/test/MC/AArch64/SVE/ucvtf.s
M llvm/test/MC/AArch64/SVE/udiv.s
M llvm/test/MC/AArch64/SVE/udivr.s
M llvm/test/MC/AArch64/SVE/udot.s
M llvm/test/MC/AArch64/SVE/umax.s
M llvm/test/MC/AArch64/SVE/umaxv.s
M llvm/test/MC/AArch64/SVE/umin.s
M llvm/test/MC/AArch64/SVE/uminv.s
M llvm/test/MC/AArch64/SVE/umulh.s
M llvm/test/MC/AArch64/SVE/uqadd.s
M llvm/test/MC/AArch64/SVE/uqdecb.s
M llvm/test/MC/AArch64/SVE/uqdecd.s
M llvm/test/MC/AArch64/SVE/uqdech.s
M llvm/test/MC/AArch64/SVE/uqdecp.s
M llvm/test/MC/AArch64/SVE/uqdecw.s
M llvm/test/MC/AArch64/SVE/uqincb.s
M llvm/test/MC/AArch64/SVE/uqincd.s
M llvm/test/MC/AArch64/SVE/uqinch.s
M llvm/test/MC/AArch64/SVE/uqincp.s
M llvm/test/MC/AArch64/SVE/uqincw.s
M llvm/test/MC/AArch64/SVE/uqsub.s
M llvm/test/MC/AArch64/SVE/uunpkhi.s
M llvm/test/MC/AArch64/SVE/uunpklo.s
M llvm/test/MC/AArch64/SVE/uxtb.s
M llvm/test/MC/AArch64/SVE/uxth.s
M llvm/test/MC/AArch64/SVE/uxtw.s
M llvm/test/MC/AArch64/SVE/uzp1.s
M llvm/test/MC/AArch64/SVE/uzp2.s
M llvm/test/MC/AArch64/SVE/whilele.s
M llvm/test/MC/AArch64/SVE/whilelo.s
M llvm/test/MC/AArch64/SVE/whilels.s
M llvm/test/MC/AArch64/SVE/whilelt.s
M llvm/test/MC/AArch64/SVE/wrffr.s
M llvm/test/MC/AArch64/SVE/zip1.s
M llvm/test/MC/AArch64/SVE/zip2.s
M llvm/test/MC/AArch64/SVE2/adclb.s
M llvm/test/MC/AArch64/SVE2/adclt.s
M llvm/test/MC/AArch64/SVE2/addhnb.s
M llvm/test/MC/AArch64/SVE2/addhnt.s
M llvm/test/MC/AArch64/SVE2/addp.s
M llvm/test/MC/AArch64/SVE2/aesd.s
M llvm/test/MC/AArch64/SVE2/aese.s
M llvm/test/MC/AArch64/SVE2/aesimc.s
M llvm/test/MC/AArch64/SVE2/aesmc.s
M llvm/test/MC/AArch64/SVE2/bcax.s
M llvm/test/MC/AArch64/SVE2/bdep.s
M llvm/test/MC/AArch64/SVE2/bext.s
M llvm/test/MC/AArch64/SVE2/bgrp.s
M llvm/test/MC/AArch64/SVE2/bsl.s
M llvm/test/MC/AArch64/SVE2/bsl1n.s
M llvm/test/MC/AArch64/SVE2/bsl2n.s
M llvm/test/MC/AArch64/SVE2/cadd.s
M llvm/test/MC/AArch64/SVE2/cdot.s
M llvm/test/MC/AArch64/SVE2/cmla.s
M llvm/test/MC/AArch64/SVE2/eor3.s
M llvm/test/MC/AArch64/SVE2/eorbt.s
M llvm/test/MC/AArch64/SVE2/eortb.s
M llvm/test/MC/AArch64/SVE2/ext.s
M llvm/test/MC/AArch64/SVE2/faddp.s
M llvm/test/MC/AArch64/SVE2/fcvtlt.s
M llvm/test/MC/AArch64/SVE2/fcvtnt.s
M llvm/test/MC/AArch64/SVE2/fcvtx.s
M llvm/test/MC/AArch64/SVE2/fcvtxnt.s
M llvm/test/MC/AArch64/SVE2/flogb.s
M llvm/test/MC/AArch64/SVE2/fmaxnmp.s
M llvm/test/MC/AArch64/SVE2/fmaxp.s
M llvm/test/MC/AArch64/SVE2/fminnmp.s
M llvm/test/MC/AArch64/SVE2/fminp.s
M llvm/test/MC/AArch64/SVE2/fmlalb.s
M llvm/test/MC/AArch64/SVE2/fmlalt.s
M llvm/test/MC/AArch64/SVE2/fmlslb.s
M llvm/test/MC/AArch64/SVE2/fmlslt.s
M llvm/test/MC/AArch64/SVE2/histcnt.s
M llvm/test/MC/AArch64/SVE2/histseg.s
M llvm/test/MC/AArch64/SVE2/ldnt1b.s
M llvm/test/MC/AArch64/SVE2/ldnt1d.s
M llvm/test/MC/AArch64/SVE2/ldnt1h.s
M llvm/test/MC/AArch64/SVE2/ldnt1sb.s
M llvm/test/MC/AArch64/SVE2/ldnt1sh.s
M llvm/test/MC/AArch64/SVE2/ldnt1sw.s
M llvm/test/MC/AArch64/SVE2/ldnt1w.s
M llvm/test/MC/AArch64/SVE2/match.s
M llvm/test/MC/AArch64/SVE2/mla.s
M llvm/test/MC/AArch64/SVE2/mls.s
M llvm/test/MC/AArch64/SVE2/mul.s
M llvm/test/MC/AArch64/SVE2/nbsl.s
M llvm/test/MC/AArch64/SVE2/nmatch.s
M llvm/test/MC/AArch64/SVE2/pmul.s
M llvm/test/MC/AArch64/SVE2/pmullb-128.s
M llvm/test/MC/AArch64/SVE2/pmullb.s
M llvm/test/MC/AArch64/SVE2/pmullt-128.s
M llvm/test/MC/AArch64/SVE2/pmullt.s
M llvm/test/MC/AArch64/SVE2/raddhnb.s
M llvm/test/MC/AArch64/SVE2/raddhnt.s
M llvm/test/MC/AArch64/SVE2/rax1.s
M llvm/test/MC/AArch64/SVE2/rshrnb.s
M llvm/test/MC/AArch64/SVE2/rshrnt.s
M llvm/test/MC/AArch64/SVE2/rsubhnb.s
M llvm/test/MC/AArch64/SVE2/rsubhnt.s
M llvm/test/MC/AArch64/SVE2/saba.s
M llvm/test/MC/AArch64/SVE2/sabalb.s
M llvm/test/MC/AArch64/SVE2/sabalt.s
M llvm/test/MC/AArch64/SVE2/sabdlb.s
M llvm/test/MC/AArch64/SVE2/sabdlt.s
M llvm/test/MC/AArch64/SVE2/sadalp.s
M llvm/test/MC/AArch64/SVE2/saddlb.s
M llvm/test/MC/AArch64/SVE2/saddlbt.s
M llvm/test/MC/AArch64/SVE2/saddlt.s
M llvm/test/MC/AArch64/SVE2/saddwb.s
M llvm/test/MC/AArch64/SVE2/saddwt.s
M llvm/test/MC/AArch64/SVE2/sbclb.s
M llvm/test/MC/AArch64/SVE2/sbclt.s
M llvm/test/MC/AArch64/SVE2/shadd.s
M llvm/test/MC/AArch64/SVE2/shrnb.s
M llvm/test/MC/AArch64/SVE2/shrnt.s
M llvm/test/MC/AArch64/SVE2/shsub.s
M llvm/test/MC/AArch64/SVE2/shsubr.s
M llvm/test/MC/AArch64/SVE2/sli.s
M llvm/test/MC/AArch64/SVE2/sm4e.s
M llvm/test/MC/AArch64/SVE2/sm4ekey.s
M llvm/test/MC/AArch64/SVE2/smaxp.s
M llvm/test/MC/AArch64/SVE2/sminp.s
M llvm/test/MC/AArch64/SVE2/smlalb.s
M llvm/test/MC/AArch64/SVE2/smlalt.s
M llvm/test/MC/AArch64/SVE2/smlslb.s
M llvm/test/MC/AArch64/SVE2/smlslt.s
M llvm/test/MC/AArch64/SVE2/smulh.s
M llvm/test/MC/AArch64/SVE2/smullb.s
M llvm/test/MC/AArch64/SVE2/smullt.s
M llvm/test/MC/AArch64/SVE2/splice.s
M llvm/test/MC/AArch64/SVE2/sqabs.s
M llvm/test/MC/AArch64/SVE2/sqadd.s
M llvm/test/MC/AArch64/SVE2/sqcadd.s
M llvm/test/MC/AArch64/SVE2/sqdmlalb.s
M llvm/test/MC/AArch64/SVE2/sqdmlalbt.s
M llvm/test/MC/AArch64/SVE2/sqdmlalt.s
M llvm/test/MC/AArch64/SVE2/sqdmlslb.s
M llvm/test/MC/AArch64/SVE2/sqdmlslbt.s
M llvm/test/MC/AArch64/SVE2/sqdmlslt.s
M llvm/test/MC/AArch64/SVE2/sqdmulh.s
M llvm/test/MC/AArch64/SVE2/sqdmullb.s
M llvm/test/MC/AArch64/SVE2/sqdmullt.s
M llvm/test/MC/AArch64/SVE2/sqneg.s
M llvm/test/MC/AArch64/SVE2/sqrdcmlah.s
M llvm/test/MC/AArch64/SVE2/sqrdmlah.s
M llvm/test/MC/AArch64/SVE2/sqrdmlsh.s
M llvm/test/MC/AArch64/SVE2/sqrdmulh.s
M llvm/test/MC/AArch64/SVE2/sqrshl.s
M llvm/test/MC/AArch64/SVE2/sqrshlr.s
M llvm/test/MC/AArch64/SVE2/sqrshrnb.s
M llvm/test/MC/AArch64/SVE2/sqrshrnt.s
M llvm/test/MC/AArch64/SVE2/sqrshrunb.s
M llvm/test/MC/AArch64/SVE2/sqrshrunt.s
M llvm/test/MC/AArch64/SVE2/sqshl.s
M llvm/test/MC/AArch64/SVE2/sqshlr.s
M llvm/test/MC/AArch64/SVE2/sqshlu.s
M llvm/test/MC/AArch64/SVE2/sqshrnb.s
M llvm/test/MC/AArch64/SVE2/sqshrnt.s
M llvm/test/MC/AArch64/SVE2/sqshrunb.s
M llvm/test/MC/AArch64/SVE2/sqshrunt.s
M llvm/test/MC/AArch64/SVE2/sqsub.s
M llvm/test/MC/AArch64/SVE2/sqsubr.s
M llvm/test/MC/AArch64/SVE2/sqxtnb.s
M llvm/test/MC/AArch64/SVE2/sqxtnt.s
M llvm/test/MC/AArch64/SVE2/sqxtunb.s
M llvm/test/MC/AArch64/SVE2/sqxtunt.s
M llvm/test/MC/AArch64/SVE2/srhadd.s
M llvm/test/MC/AArch64/SVE2/sri.s
M llvm/test/MC/AArch64/SVE2/srshl.s
M llvm/test/MC/AArch64/SVE2/srshlr.s
M llvm/test/MC/AArch64/SVE2/srshr.s
M llvm/test/MC/AArch64/SVE2/srsra.s
M llvm/test/MC/AArch64/SVE2/sshllb.s
M llvm/test/MC/AArch64/SVE2/sshllt.s
M llvm/test/MC/AArch64/SVE2/ssra.s
M llvm/test/MC/AArch64/SVE2/ssublb.s
M llvm/test/MC/AArch64/SVE2/ssublbt.s
M llvm/test/MC/AArch64/SVE2/ssublt.s
M llvm/test/MC/AArch64/SVE2/ssubltb.s
M llvm/test/MC/AArch64/SVE2/ssubwb.s
M llvm/test/MC/AArch64/SVE2/ssubwt.s
M llvm/test/MC/AArch64/SVE2/stnt1b.s
M llvm/test/MC/AArch64/SVE2/stnt1d.s
M llvm/test/MC/AArch64/SVE2/stnt1h.s
M llvm/test/MC/AArch64/SVE2/stnt1w.s
M llvm/test/MC/AArch64/SVE2/subhnb.s
M llvm/test/MC/AArch64/SVE2/subhnt.s
M llvm/test/MC/AArch64/SVE2/suqadd.s
M llvm/test/MC/AArch64/SVE2/tbl.s
M llvm/test/MC/AArch64/SVE2/tbx.s
M llvm/test/MC/AArch64/SVE2/uaba.s
M llvm/test/MC/AArch64/SVE2/uabalb.s
M llvm/test/MC/AArch64/SVE2/uabalt.s
M llvm/test/MC/AArch64/SVE2/uabdlb.s
M llvm/test/MC/AArch64/SVE2/uabdlt.s
M llvm/test/MC/AArch64/SVE2/uadalp.s
M llvm/test/MC/AArch64/SVE2/uaddlb.s
M llvm/test/MC/AArch64/SVE2/uaddlt.s
M llvm/test/MC/AArch64/SVE2/uaddwb.s
M llvm/test/MC/AArch64/SVE2/uaddwt.s
M llvm/test/MC/AArch64/SVE2/uhadd.s
M llvm/test/MC/AArch64/SVE2/uhsub.s
M llvm/test/MC/AArch64/SVE2/uhsubr.s
M llvm/test/MC/AArch64/SVE2/umaxp.s
M llvm/test/MC/AArch64/SVE2/uminp.s
M llvm/test/MC/AArch64/SVE2/umlalb.s
M llvm/test/MC/AArch64/SVE2/umlalt.s
M llvm/test/MC/AArch64/SVE2/umlslb.s
M llvm/test/MC/AArch64/SVE2/umlslt.s
M llvm/test/MC/AArch64/SVE2/umulh.s
M llvm/test/MC/AArch64/SVE2/umullb.s
M llvm/test/MC/AArch64/SVE2/umullt.s
M llvm/test/MC/AArch64/SVE2/uqadd.s
M llvm/test/MC/AArch64/SVE2/uqrshl.s
M llvm/test/MC/AArch64/SVE2/uqrshlr.s
M llvm/test/MC/AArch64/SVE2/uqrshrnb.s
M llvm/test/MC/AArch64/SVE2/uqrshrnt.s
M llvm/test/MC/AArch64/SVE2/uqshl.s
M llvm/test/MC/AArch64/SVE2/uqshlr.s
M llvm/test/MC/AArch64/SVE2/uqshrnb.s
M llvm/test/MC/AArch64/SVE2/uqshrnt.s
M llvm/test/MC/AArch64/SVE2/uqsub.s
M llvm/test/MC/AArch64/SVE2/uqsubr.s
M llvm/test/MC/AArch64/SVE2/uqxtnb.s
M llvm/test/MC/AArch64/SVE2/uqxtnt.s
M llvm/test/MC/AArch64/SVE2/urecpe.s
M llvm/test/MC/AArch64/SVE2/urhadd.s
M llvm/test/MC/AArch64/SVE2/urshl.s
M llvm/test/MC/AArch64/SVE2/urshlr.s
M llvm/test/MC/AArch64/SVE2/urshr.s
M llvm/test/MC/AArch64/SVE2/ursqrte.s
M llvm/test/MC/AArch64/SVE2/ursra.s
M llvm/test/MC/AArch64/SVE2/ushllb.s
M llvm/test/MC/AArch64/SVE2/ushllt.s
M llvm/test/MC/AArch64/SVE2/usqadd.s
M llvm/test/MC/AArch64/SVE2/usra.s
M llvm/test/MC/AArch64/SVE2/usublb.s
M llvm/test/MC/AArch64/SVE2/usublt.s
M llvm/test/MC/AArch64/SVE2/usubwb.s
M llvm/test/MC/AArch64/SVE2/usubwt.s
M llvm/test/MC/AArch64/SVE2/whilege.s
M llvm/test/MC/AArch64/SVE2/whilegt.s
M llvm/test/MC/AArch64/SVE2/whilehi.s
M llvm/test/MC/AArch64/SVE2/whilehs.s
M llvm/test/MC/AArch64/SVE2/whilerw.s
M llvm/test/MC/AArch64/SVE2/whilewr.s
M llvm/test/MC/AArch64/SVE2/xar.s
M llvm/test/MC/AArch64/adrp-annotation.s
M llvm/test/MC/AArch64/arm32-elf-relocs.s
M llvm/test/MC/AArch64/arm64-compact-unwind-fallback.s
M llvm/test/MC/AArch64/arm64-elf-relocs.s
M llvm/test/MC/AArch64/arm64-leaf-compact-unwind.s
M llvm/test/MC/AArch64/coff-relocations.s
M llvm/test/MC/AArch64/darwin-reloc-addsubimm.s
M llvm/test/MC/AArch64/elf-reloc-addsubimm.s
M llvm/test/MC/AArch64/optional-hash.s
M llvm/test/MC/AMDGPU/branch-comment.s
M llvm/test/MC/AMDGPU/data.s
M llvm/test/MC/AMDGPU/labels-branch-gfx9.s
M llvm/test/MC/AMDGPU/labels-branch.s
M llvm/test/MC/AMDGPU/offsetbug_once.s
M llvm/test/MC/AMDGPU/offsetbug_one_and_one.s
M llvm/test/MC/AMDGPU/offsetbug_twice.s
M llvm/test/MC/AMDGPU/s_endpgm.s
M llvm/test/MC/ARM/AlignedBundling/group-bundle-arm.s
M llvm/test/MC/ARM/AlignedBundling/pad-align-to-bundle-end.s
M llvm/test/MC/ARM/AlignedBundling/subtarget-change.s
M llvm/test/MC/ARM/Windows/mov32t-range.s
M llvm/test/MC/ARM/align_arm_2_thumb.s
M llvm/test/MC/ARM/align_thumb_2_arm.s
M llvm/test/MC/ARM/aligned-blx.s
M llvm/test/MC/ARM/assembler-fill.s
M llvm/test/MC/ARM/branch-disassemble.s
M llvm/test/MC/ARM/cmp-immediate-fixup.s
M llvm/test/MC/ARM/cmp-immediate-fixup2.s
M llvm/test/MC/ARM/coff-relocations.s
M llvm/test/MC/ARM/dwarf-asm-multiple-sections-dwarf-2.s
M llvm/test/MC/ARM/dwarf-asm-no-code.s
M llvm/test/MC/ARM/dwarf-asm-nonstandard-section.s
M llvm/test/MC/ARM/dwarf-asm-single-section.s
M llvm/test/MC/ARM/ehabi-personality-abs.s
M llvm/test/MC/ARM/elf-movt.s
M llvm/test/MC/ARM/fixup-cpu-mode.s
M llvm/test/MC/ARM/inst-directive-other.s
M llvm/test/MC/ARM/macho-reloc-thumb-local.s
M llvm/test/MC/ARM/macho-word-reloc-thumb.s
M llvm/test/MC/ARM/modified-immediate-fixup.s
M llvm/test/MC/ARM/symbol-variants.s
M llvm/test/MC/ARM/t2-modified-immediate-fixup.s
M llvm/test/MC/ARM/thumb-cb-thumbfunc.s
M llvm/test/MC/ARM/thumb1-relax-bcc.s
M llvm/test/MC/ARM/thumb1-relax-br.s
M llvm/test/MC/ARM/thumb2-cbn-to-next-inst.s
M llvm/test/MC/ARM/tls-directives.s
M llvm/test/MC/AVR/dwarf-asm-no-code.s
M llvm/test/MC/AVR/inst-adc.s
M llvm/test/MC/AVR/inst-add.s
M llvm/test/MC/AVR/inst-adiw.s
M llvm/test/MC/AVR/inst-and.s
M llvm/test/MC/AVR/inst-andi.s
M llvm/test/MC/AVR/inst-bld.s
M llvm/test/MC/AVR/inst-break.s
M llvm/test/MC/AVR/inst-bst.s
M llvm/test/MC/AVR/inst-cbr.s
M llvm/test/MC/AVR/inst-clr.s
M llvm/test/MC/AVR/inst-cp.s
M llvm/test/MC/AVR/inst-cpc.s
M llvm/test/MC/AVR/inst-cpi.s
M llvm/test/MC/AVR/inst-cpse.s
M llvm/test/MC/AVR/inst-des.s
M llvm/test/MC/AVR/inst-eicall.s
M llvm/test/MC/AVR/inst-eijmp.s
M llvm/test/MC/AVR/inst-eor.s
M llvm/test/MC/AVR/inst-family-set-clr-flag.s
M llvm/test/MC/AVR/inst-icall.s
M llvm/test/MC/AVR/inst-ijmp.s
M llvm/test/MC/AVR/inst-ldi.s
M llvm/test/MC/AVR/inst-lsl.s
M llvm/test/MC/AVR/inst-mov.s
M llvm/test/MC/AVR/inst-nop.s
M llvm/test/MC/AVR/inst-or.s
M llvm/test/MC/AVR/inst-ori.s
M llvm/test/MC/AVR/inst-ret.s
M llvm/test/MC/AVR/inst-reti.s
M llvm/test/MC/AVR/inst-rol.s
M llvm/test/MC/AVR/inst-sbc.s
M llvm/test/MC/AVR/inst-sbci.s
M llvm/test/MC/AVR/inst-sbiw.s
M llvm/test/MC/AVR/inst-sbr.s
M llvm/test/MC/AVR/inst-ser.s
M llvm/test/MC/AVR/inst-sleep.s
M llvm/test/MC/AVR/inst-sub.s
M llvm/test/MC/AVR/inst-subi.s
M llvm/test/MC/AVR/inst-tst.s
M llvm/test/MC/AVR/inst-wdr.s
M llvm/test/MC/AVR/relocations-abs.s
M llvm/test/MC/AsmParser/directive_fill_2.s
M llvm/test/MC/BPF/insn-unit-32.s
M llvm/test/MC/BPF/insn-unit.s
M llvm/test/MC/BPF/load-store-32.s
M llvm/test/MC/Disassembler/ARM/mve-lol.txt
M llvm/test/MC/ELF/relax-all-flag.s
M llvm/test/MC/Hexagon/J2_trap1_dep.s
M llvm/test/MC/Hexagon/align.s
M llvm/test/MC/Hexagon/cmpyrw.s
M llvm/test/MC/Hexagon/extensions/v67_hvx.s
M llvm/test/MC/Hexagon/extensions/v67t_audio.s
M llvm/test/MC/Hexagon/hvx-double-implies-hvx.s
M llvm/test/MC/Hexagon/hvx-swapped-regpairs.s
M llvm/test/MC/Hexagon/quad_regs.s
M llvm/test/MC/Hexagon/smallcore_dis.s
M llvm/test/MC/Hexagon/v60-alu.s
M llvm/test/MC/Hexagon/v60-misc.s
M llvm/test/MC/Hexagon/v60-permute.s
M llvm/test/MC/Hexagon/v60-shift.s
M llvm/test/MC/Hexagon/v60-vcmp.s
M llvm/test/MC/Hexagon/v60-vmem.s
M llvm/test/MC/Hexagon/v60-vmpy-acc.s
M llvm/test/MC/Hexagon/v60-vmpy1.s
M llvm/test/MC/Hexagon/v60lookup.s
M llvm/test/MC/Hexagon/v62_all.s
M llvm/test/MC/Hexagon/v62_jumps.s
M llvm/test/MC/Hexagon/v62a.s
M llvm/test/MC/Hexagon/v65_all.s
M llvm/test/MC/Hexagon/v66.s
M llvm/test/MC/Hexagon/v67.s
M llvm/test/MC/Hexagon/v67_all.s
M llvm/test/MC/Hexagon/z-instructions.s
M llvm/test/MC/MSP430/opcode.s
M llvm/test/MC/MachO/ARM/compact-unwind-armv7k.s
M llvm/test/MC/MachO/ARM/llvm-objdump-macho-stripped.s
M llvm/test/MC/MachO/ARM/llvm-objdump-macho.s
M llvm/test/MC/MachO/ARM/no-tls-assert.ll
M llvm/test/MC/MachO/darwin-sdk-version.ll
M llvm/test/MC/MachO/darwin-version-min-load-command.s
M llvm/test/MC/Mips/cfi-encoding.s
M llvm/test/MC/Mips/cpload.s
M llvm/test/MC/Mips/cplocal.s
M llvm/test/MC/Mips/cprestore-noreorder-noat.s
M llvm/test/MC/Mips/cprestore-noreorder.s
M llvm/test/MC/Mips/cprestore-reorder.s
M llvm/test/MC/Mips/cpsetup.s
M llvm/test/MC/Mips/expansion-j-sym-pic.s
M llvm/test/MC/Mips/expansion-jal-sym-pic.s
M llvm/test/MC/Mips/higher-highest-addressing.s
M llvm/test/MC/Mips/hilo-addressing.s
M llvm/test/MC/Mips/micromips-neg-offset.s
M llvm/test/MC/Mips/mips64extins.s
M llvm/test/MC/Mips/mips64shift.ll
M llvm/test/MC/Mips/mips_gprel16.s
M llvm/test/MC/Mips/nacl-mask.s
M llvm/test/MC/Mips/sext_64_32.ll
M llvm/test/MC/PowerPC/ppc64-prefix-align-labels.s
M llvm/test/MC/PowerPC/ppc64-prefix-align.s
M llvm/test/MC/RISCV/cnop.s
M llvm/test/MC/RISCV/compress-cjal.s
M llvm/test/MC/RISCV/compress-rv32d.s
M llvm/test/MC/RISCV/compress-rv32f.s
M llvm/test/MC/RISCV/compress-rv32i.s
M llvm/test/MC/RISCV/compress-rv64i.s
M llvm/test/MC/RISCV/csr-aliases.s
M llvm/test/MC/RISCV/fixups-compressed.s
M llvm/test/MC/RISCV/function-call.s
M llvm/test/MC/RISCV/hilo-constaddr-expr.s
M llvm/test/MC/RISCV/hilo-constaddr.s
M llvm/test/MC/RISCV/numeric-reg-names-d.s
M llvm/test/MC/RISCV/numeric-reg-names-f.s
M llvm/test/MC/RISCV/option-mix.s
M llvm/test/MC/RISCV/option-pushpop.s
M llvm/test/MC/RISCV/option-rvc.s
M llvm/test/MC/RISCV/pseudo-jump.s
M llvm/test/MC/RISCV/rv32-relaxation.s
M llvm/test/MC/RISCV/rv32a-valid.s
M llvm/test/MC/RISCV/rv32c-only-valid.s
M llvm/test/MC/RISCV/rv32c-valid.s
M llvm/test/MC/RISCV/rv32d-valid.s
M llvm/test/MC/RISCV/rv32dc-valid.s
M llvm/test/MC/RISCV/rv32e-invalid.s
M llvm/test/MC/RISCV/rv32f-valid.s
M llvm/test/MC/RISCV/rv32fc-aliases-valid.s
M llvm/test/MC/RISCV/rv32fc-valid.s
M llvm/test/MC/RISCV/rv32m-valid.s
M llvm/test/MC/RISCV/rv64-relaxation.s
M llvm/test/MC/RISCV/rv64a-aliases-valid.s
M llvm/test/MC/RISCV/rv64a-valid.s
M llvm/test/MC/RISCV/rv64c-valid.s
M llvm/test/MC/RISCV/rv64d-aliases-valid.s
M llvm/test/MC/RISCV/rv64d-valid.s
M llvm/test/MC/RISCV/rv64dc-valid.s
M llvm/test/MC/RISCV/rv64f-aliases-valid.s
M llvm/test/MC/RISCV/rv64f-valid.s
M llvm/test/MC/RISCV/rv64m-valid.s
M llvm/test/MC/RISCV/rva-aliases-valid.s
M llvm/test/MC/RISCV/rvd-aliases-valid.s
M llvm/test/MC/RISCV/rvdc-aliases-valid.s
M llvm/test/MC/RISCV/rvf-aliases-valid.s
M llvm/test/MC/RISCV/rvf-user-csr-names.s
M llvm/test/MC/RISCV/tail-call.s
M llvm/test/MC/SystemZ/directive-insn.s
M llvm/test/MC/WebAssembly/objdump.s
M llvm/test/MC/X86/AlignedBundling/autogen-inst-offset-align-to-end.s
M llvm/test/MC/X86/AlignedBundling/autogen-inst-offset-padding.s
M llvm/test/MC/X86/AlignedBundling/different-sections.s
M llvm/test/MC/X86/AlignedBundling/labeloffset.s
M llvm/test/MC/X86/AlignedBundling/long-nop-pad.s
M llvm/test/MC/X86/AlignedBundling/misaligned-bundle-group.s
M llvm/test/MC/X86/AlignedBundling/misaligned-bundle.s
M llvm/test/MC/X86/AlignedBundling/nesting.s
M llvm/test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s
M llvm/test/MC/X86/AlignedBundling/pad-bundle-groups.s
M llvm/test/MC/X86/AlignedBundling/relax-at-bundle-end.s
M llvm/test/MC/X86/AlignedBundling/relax-in-bundle-group.s
M llvm/test/MC/X86/AlignedBundling/rodata-section.s
M llvm/test/MC/X86/AlignedBundling/single-inst-bundling.s
M llvm/test/MC/X86/compact-unwind.s
M llvm/test/MC/X86/data-prefix16.s
M llvm/test/MC/X86/data-prefix32.s
M llvm/test/MC/X86/data-prefix64.s
M llvm/test/MC/X86/faultmap-section-parsing.s
M llvm/test/MC/X86/return-column.s
M llvm/test/MC/X86/tlsdesc-32.s
M llvm/test/MC/X86/tlsdesc-64.s
M llvm/test/MC/X86/x86-branch-relaxation.s
M llvm/test/MC/X86/x86_long_nop.s
M llvm/test/Object/AMDGPU/objdump.s
M llvm/test/Object/ARM/macho-data-in-code.test
M llvm/test/Object/ARM/objdump-thumb.test
M llvm/test/Object/Mips/feature.test
M llvm/test/Object/X86/macho-text-sections.test
M llvm/test/Object/X86/objdump-disassembly-inline-relocations.test
M llvm/test/Object/X86/objdump-trivial-object.test
M llvm/test/Object/elf-invalid-phdr.test
M llvm/test/Object/invalid.test
M llvm/test/Object/macho-invalid.test
M llvm/test/Object/objdump-export-list.test
M llvm/test/Object/objdump-relocations.test
M llvm/test/Object/objdump-section-content.test
M llvm/test/Object/objdump-symbol-table.test
M llvm/test/ObjectYAML/CodeView/sections.yaml
M llvm/test/tools/gold/X86/v1.16/wrap-2.ll
M llvm/test/tools/llvm-objcopy/COFF/remove-section.test
M llvm/test/tools/llvm-objdump/ELF/call-absolute-symbol.test
M llvm/test/tools/llvm-objdump/MachO/AArch64/macho-fat-arm-disasm.test
M llvm/test/tools/llvm-objdump/MachO/disassemble-g-dsym.test
M llvm/test/tools/llvm-objdump/X86/elf-disassemble-relocs.test
M llvm/test/tools/llvm-objdump/X86/elf-disassemble.test
M llvm/test/tools/llvm-objdump/embedded-source.test
Log Message:
-----------
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
As announced here: http://lists.llvm.org/pipermail/llvm-dev/2019-April/131786.html
Grouped option syntax (POSIX Utility Conventions) does not play well with -long-option
A subsequent change will reject -long-option.
More information about the All-commits
mailing list