[all-commits] [llvm/llvm-project] 755e00: [X86] Remove isel patterns for X86VBroadcast+trunc...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 755e00876cd383785668e88c871c4e4ef9b648a9
      https://github.com/llvm/llvm-project/commit/755e00876cd383785668e88c871c4e4ef9b648a9
  Author: Craig Topper <craig.topper at gmail.com>
  Date:   2020-03-13 (Fri, 13 Mar 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86InstrAVX512.td
    M llvm/lib/Target/X86/X86InstrSSE.td
    M llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
    M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
    M llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll

  Log Message:
  -----------
  [X86] Remove isel patterns for X86VBroadcast+trunc+extload. Replace with DAG combines.

This is a little more complicated than I'd like it to be. We have
to manually match a trunc+srl+load pattern that generic DAG
combine won't do for us due to isTypeDesirableForOp.