[all-commits] [llvm/llvm-project] 2c6c16: [ARM] Optimise ASRL/LSRL to smaller shifts using d...

[David Green via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 2c6c169dbd6041b4575b2234c532aad50a472e81
      https://github.com/llvm/llvm-project/commit/2c6c169dbd6041b4575b2234c532aad50a472e81
  Author: David Green <david.green at arm.com>
  Date:   2020-03-13 (Fri, 13 Mar 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.h
    M llvm/test/CodeGen/Thumb2/fir.ll
    M llvm/test/CodeGen/Thumb2/shift_parts.ll

  Log Message:
  -----------
  [ARM] Optimise ASRL/LSRL to smaller shifts using demand bits.

The ASRL/LSRL long shifts are generated from 64bit shifts. Once we have
them, it might turn out that enough of the 64bit result was not required
that we can use a smaller shift to perform the same result. As the
smaller shift can in general be folded in more way, such as into add
instructions in one of the test cases here, we can use the demand bit
analysis to prefer the smaller shifts where we can.

Differential Revision: https://reviews.llvm.org/D75371