[all-commits] [llvm/llvm-project] e91fee: [AMDGPU] Add ISD::FSHR -> ALIGNBIT support

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: e91feeed21ee16abdb73f6e8cd471a253136e2cf
      https://github.com/llvm/llvm-project/commit/e91feeed21ee16abdb73f6e8cd471a253136e2cf
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-03-12 (Thu, 12 Mar 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
    M llvm/lib/Target/AMDGPU/EvergreenInstructions.td
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
    M llvm/test/CodeGen/AMDGPU/fshl.ll
    M llvm/test/CodeGen/AMDGPU/fshr.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/permute.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
    M llvm/test/CodeGen/AMDGPU/shift-i128.ll

  Log Message:
  -----------
  [AMDGPU] Add ISD::FSHR -> ALIGNBIT support

This patch allows ISD::FSHR(i32) patterns to lower to ALIGNBIT instructions.

This improves test coverage of ISD::FSHR matching - x86 has both FSHL/FSHR instructions and we prefer FSHL by default.

Differential Revision: https://reviews.llvm.org/D76070