[all-commits] [llvm/llvm-project] b3b472: [X86] Replace (most) X86ISD::SHLD/SHRD usage with ...
Simon Pilgrim via All-commits
all-commits at lists.llvm.org
Wed Mar 11 04:33:24 PDT 2020
Branch: refs/heads/master
Home: https://github.com/llvm/llvm-project
Commit: b3b4727a3e7e170189e58ee8a6409112839a87b0
https://github.com/llvm/llvm-project/commit/b3b4727a3e7e170189e58ee8a6409112839a87b0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2020-03-11 (Wed, 11 Mar 2020)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrInfo.td
M llvm/lib/Target/X86/X86InstrShiftRotate.td
M llvm/test/CodeGen/X86/clear-highbits.ll
M llvm/test/CodeGen/X86/clear-lowbits.ll
M llvm/test/CodeGen/X86/extract-bits.ll
M llvm/test/CodeGen/X86/extract-lowbits.ll
M llvm/test/CodeGen/X86/fshl.ll
M llvm/test/CodeGen/X86/fshr.ll
M llvm/test/CodeGen/X86/shift-combine.ll
M llvm/test/CodeGen/X86/shift-parts.ll
Log Message:
-----------
[X86] Replace (most) X86ISD::SHLD/SHRD usage with ISD::FSHL/FSHR generic opcodes (PR39467)
For i32 and i64 cases, X86ISD::SHLD/SHRD are close enough to ISD::FSHL/FSHR that we can use them directly, we just need to account for the operand commutation for SHRD.
The i16 SHLD/SHRD case is annoying as the shift amount is modulo-32 (vs funnel shift modulo-16), so I've added X86ISD::FSHL/FSHR equivalents, which matches the generic implementation in all other terms.
Something I'm slightly concerned with is that ISD::FSHL/FSHR legality is controlled by the Subtarget.isSHLDSlow() feature flag - we don't normally use non-ISA features for this but it allows the DAG combines to continue to operate after legalization in a lot more cases.
The X86 *bits.ll changes are all affected by the same issue - we now have a "FSHR(-1,-1,amt) -> ROTR(-1,amt) -> (-1)" simplification that reduces the dependencies enough for the branch fall through code to mess up.
Differential Revision: https://reviews.llvm.org/D75748
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