[all-commits] [llvm/llvm-project] b17a81: GlobalISel: Add missing add/sub with carries to Ma...

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: b17a81f8b23b8412c1fa663c9bbe60060a494503
      https://github.com/llvm/llvm-project/commit/b17a81f8b23b8412c1fa663c9bbe60060a494503
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-03-10 (Tue, 10 Mar 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
    M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
    M llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp

  Log Message:
  -----------
  GlobalISel: Add missing add/sub with carries to MachineIRBuilder