[all-commits] [llvm/llvm-project] c7b2e7: [AMDGPU] Fix scheduling info for terminator SALU i...

[jayfoad via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c7b2e7f52742add7444fba2c04e4fa60b3ea4813
      https://github.com/llvm/llvm-project/commit/c7b2e7f52742add7444fba2c04e4fa60b3ea4813
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2020-03-09 (Mon, 09 Mar 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstructions.td

  Log Message:
  -----------
  [AMDGPU] Fix scheduling info for terminator SALU instructions

Summary:
Instruction variants like S_MOV_B32_term should have the same SchedRW
class as the base instruction, S_MOV_B32. This probably doesn't make any
difference in practice because as terminators, they'll always be
scheduled at the end of a basic block, but it's simply more correct than
giving them all the default SchedRW class of Write32Bit, which implies a
VALU operation.

Reviewers: rampitec, arsenm, nhaehnle

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75860