[all-commits] [llvm/llvm-project] 3dcc0d: [X86] Teach combineToExtendBoolVectorInReg to crea...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 3dcc0db15e372df2e6c61873dc2d8a2f780cd27e
      https://github.com/llvm/llvm-project/commit/3dcc0db15e372df2e6c61873dc2d8a2f780cd27e
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-03-09 (Mon, 09 Mar 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
    M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
    M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
    M llvm/test/CodeGen/X86/vector-sext.ll

  Log Message:
  -----------
  [X86] Teach combineToExtendBoolVectorInReg to create opportunities for using broadcast load instructions.

If we're inserting a scalar that is smaller than the element
size of the final VT, the value of the extra bits doesn't matter.

Previously we any_extended in the scalar domain before inserting.

This patch changes this to use a broadcast of the original
scalar type and then a bitcast to the final type. This might
enable the use of a broadcast load.

This recovers regressions from 07d68c24aa19483e44db4336b0935b00a5d69949
and 9fcd212e2f678fdbdf304399a1e58ca490dc54d1 without relying on
alignment of the load.

Differential Revision: https://reviews.llvm.org/D75835