[all-commits] [llvm/llvm-project] c3d981: [RISCV] Add new SchedRead SchedWrite

[ShivaChen via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c3d981aebaba1f9e0bc6a60e913ae71762b65496
      https://github.com/llvm/llvm-project/commit/c3d981aebaba1f9e0bc6a60e913ae71762b65496
  Author: Shiva Chen <shiva at andestech.com>
  Date:   2020-03-10 (Tue, 10 Mar 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/lib/Target/RISCV/RISCVSchedRocket32.td
    M llvm/lib/Target/RISCV/RISCVSchedRocket64.td
    M llvm/lib/Target/RISCV/RISCVSchedule.td

  Log Message:
  -----------
  [RISCV] Add new SchedRead SchedWrite

The patch fixes some typos and introduces ReadFMemBase, ReadFSGNJ32,
ReadFSGNJ64, WriteFSGNJ32, WriteFSGNJ64, ReadFMinMax32, ReadFMinMax64,
WriteFMinMax32, WriteFMinMax64, so the target CPU with different pipeline model
could use them to describe latency.

Differential Revision: https://reviews.llvm.org/D75515