[all-commits] [llvm/llvm-project] d81d45: [X86] Add DAG combine to replace vXi64 vzext_movl+...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: d81d451442d758dcd4f8d59162cf46c8386bef2d
      https://github.com/llvm/llvm-project/commit/d81d451442d758dcd4f8d59162cf46c8386bef2d
  Author: Craig Topper <craig.topper at gmail.com>
  Date:   2020-03-07 (Sat, 07 Mar 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86InstrAVX512.td
    M llvm/lib/Target/X86/X86InstrSSE.td
    M llvm/test/CodeGen/X86/buildvec-extract.ll
    M llvm/test/CodeGen/X86/pshufb-mask-comments.ll
    M llvm/test/CodeGen/X86/vec_set-A.ll
    M llvm/test/CodeGen/X86/vec_set-B.ll
    M llvm/test/CodeGen/X86/vector-lzcnt-128.ll
    M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
    M llvm/test/CodeGen/X86/vector-tzcnt-128.ll

  Log Message:
  -----------
  [X86] Add DAG combine to replace vXi64 vzext_movl+scalar_to_vector with vYi32 vzext_movl+scalar_to_vector if the upper 32 bits of the scalar are zero.

We can just use a 32-bit copy and zero in the SSE domain when we
zero the upper bits.

Remove an isel pattern that becomes dead with this.