[all-commits] [llvm/llvm-project] 810127: [ARM, MVE] Add the `vsbciq` intrinsics.

[Simon Tatham via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 810127f6ab5d5d7e7d6b8c3ae0b96f2027437ca8
      https://github.com/llvm/llvm-project/commit/810127f6ab5d5d7e7d6b8c3ae0b96f2027437ca8
  Author: Simon Tatham <simon.tatham at arm.com>
  Date:   2020-03-04 (Wed, 04 Mar 2020)

  Changed paths:
    M clang/include/clang/Basic/arm_mve.td
    M clang/test/CodeGen/arm-mve-intrinsics/vadc.c
    M llvm/include/llvm/IR/IntrinsicsARM.td
    M llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
    M llvm/test/CodeGen/Thumb2/mve-intrinsics/vadc.ll

  Log Message:
  -----------
  [ARM,MVE] Add the `vsbciq` intrinsics.

Summary:
These are exactly parallel to the existing `vadciq` intrinsics, which
we implemented last year as part of the original MVE intrinsics
framework setup.

Just like VADC/VADCI, the MVE VSBC/VSBCI instructions deliver two
outputs, both of which the intrinsic exposes: a modified vector
register and a carry flag. So they have to be instruction-selected in
C++ rather than Tablegen. However, in this case, that's trivial: the
same C++ isel routine we already have for VADC works unchanged, and
all we have to do is to pass it a different instruction id.

Reviewers: MarkMurrayARM, dmgreen, miyuki, ostannard

Reviewed By: miyuki

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D75444


  Commit: 068b2f313c7d27d9f6445df12d4d45d2d8c00898
      https://github.com/llvm/llvm-project/commit/068b2f313c7d27d9f6445df12d4d45d2d8c00898
  Author: Simon Tatham <simon.tatham at arm.com>
  Date:   2020-03-04 (Wed, 04 Mar 2020)

  Changed paths:
    M clang/include/clang/Basic/arm_mve.td
    A clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
    M llvm/include/llvm/IR/IntrinsicsARM.td
    M llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
    A llvm/test/CodeGen/Thumb2/mve-intrinsics/vshlc.ll

  Log Message:
  -----------
  [ARM,MVE] Add the `vshlcq` intrinsics.

Summary:
The VSHLC instruction performs a left shift of a whole vector register
by an immediate shift count up to 32, shifting in new bits at the low
end from a GPR and delivering the shifted-out bits from the high end
back into the same GPR.

Since the instruction produces two outputs (the shifted vector
register and the output GPR of shifted-out bits), it has to be
instruction-selected in C++ rather than Tablegen.

Reviewers: MarkMurrayARM, dmgreen, miyuki, ostannard

Reviewed By: miyuki

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D75445


Compare: https://github.com/llvm/llvm-project/compare/9284abd0040a...068b2f313c7d