[all-commits] [llvm/llvm-project] 02f03a: [X86] Match vpmullq latency to uops.info. Correct ...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 02f03a6fd4cd64730e6229e0202404d90079b8d1
      https://github.com/llvm/llvm-project/commit/02f03a6fd4cd64730e6229e0202404d90079b8d1
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-03-03 (Tue, 03 Mar 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86SchedSkylakeServer.td
    M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512dq.s
    M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512dqvl.s

  Log Message:
  -----------
  [X86] Match vpmullq latency to uops.info. Correct port usage for 512-bit memory form

uops.info says these should be 15 cycle instructions. Uops.info also shows the 512-bit form uses port 0 and 5 for both register and memory. We had memory using 0 and 1.

Differential Revision: https://reviews.llvm.org/D75549