[all-commits] [llvm/llvm-project] 0cd671: [DAGCombiner][X86] Disable narrowExtractedVectorLo...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 0cd6712a7af0fa2702b5d4cc733500eb5e62e7d0
      https://github.com/llvm/llvm-project/commit/0cd6712a7af0fa2702b5d4cc733500eb5e62e7d0
  Author: Craig Topper <craig.topper at gmail.com>
  Date:   2020-03-01 (Sun, 01 Mar 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/X86/avx512-extract-subvector-load-store.ll
    M llvm/test/CodeGen/X86/avx512-mask-op.ll
    M llvm/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll

  Log Message:
  -----------
  [DAGCombiner][X86] Disable narrowExtractedVectorLoad if the element type size isn't byte sized

The address calculation for the offset assumes that you can calculate the offset by multiplying the index by the store size of the element. But that only works if the element's store size is exactly its real size since we store vectors tightly packed in memory. There are improvements we could make to this like special casing extracting element 0. I think we could also handle cases where the extracted VT is byte sized and the index is aligned with the extract element count.

Differential Revision: https://reviews.llvm.org/D75377